Book excerpt: SRAM and SDRAM controllers for FPGAs, part 1

This excerpt from Embedded SOPC Design with Nios II Processor and Verilog Examples by Pong P. Chu appears courtesy of the editors at John Wiley & Sons Inc.

While an FPGA device contains dedicated memory modules within the chip, its capacity is relatively small. Separate external memory devices are needed to support the larger storage requirement. In this chapter, we provide an overview of various types of memory and discuss the design and use of a memory controller, which is the circuit to read and write the external memory devices. Since the off-chip access introduces new types of delays, we also provide a brief overview of timing issues and clock management.

16.3 OVERVIEW OF SRAM
SRAM (static random access memory) is a type of semiconductor memory. The term "static" indicates that the data are retained as long as power is being supplied and thus not changed "dynamically."

16.3.1 SRAM cell
The basic organization of an SRAM cell is shown on the top right corner of Figure 16.4. The two invertors form a latch that stores one bit of information and the two pass transistors function like switches that can be either "closed" (i.e., short circuit) or "open" (i.e. open circuit). The two pass transistors are controlled by a signal commonly referred to as word line. When the word line signal is high, the cell is enabled for access and the latch is connected to the data lines, labeled bit line e and bit line. As the label indicated, bit line always carries the complemented value of bit line. Although the bit line line is not strictly needed, it is used to improve the noise margins and thus increase the reliability. The bit line and bit line are shown as a single line in the cell array in Figure 16.4. In a read operation, the stored data are connected to the two bit lines and passed to a sense amplifier to generate the final value. In a write operation, the desired value and its complement are placed on bit line and bit line to set the latch to the desired value.



16.3.2 Basic organization
The memory cells on a memory device are usually arranged as a rectangular matrix and use two-dimensional decoding and multiplexing to access the designated cell. The conceptual diagram of a 256-by-1 SRAM (i.e., 256 (2⁸) address locations with one bit in each location) is shown in Figure 16.4. The SRAM cells are arranged as a 16-by-16-array. The address bus, addr, is split into two parts. The 4 MSBs are connected to the row decoder and the 4 LSBs are connected to the column multiplexer and decoder. The row decoder is a 4-to-2⁴ binary decoder and enables a single row of the cell array. In a read operation, the row's 16 bits of data are retrieved and passed to the 16-by-1 column multiplexer. The desired bit is selected according to the 4 LSBs of addr and routed to the 1/0 buffer. The column decoder is also a 4-to-2⁴ binary decoder. In a write operation, it enables a single cell from the selected row and the data are stored into that cell. The cell array and column multiplexer and decoder can be duplicated multiple times to support a wider data width.

To save I/O pins from a chip, the read data and write data usually share the same physical pins. An I/O buffer is associated with each pin. It contains tristate buffers and control logic to coordinate the bidirectional operation.

In addition to the address and data buses, a typical SRAM chip contains at least three control signals. These signal are:

• ce_n (chip enable or chip select): disables or enables the chip
• we_n (write enable): disables or enables the write operation
• oe_n (output enable): disables or enables the output

All these signals are active low and the _n suffix is used to emphasize this property. The functional table is shown in Table 16.1. The ce_n signal can be used to accommodate memory expansion, and the we_n and oe_n signals are used for write and read operations.