Design Article
Book excerpt: SRAM and SDRAM controllers for FPGAs, part 1
Pong Chu
8/13/2012 12:55 PM EDT
16.3.3 Timing
Our discussion in Part I focuses on the synchronous system, in which the registers are driven by the same clock signals and the input signals are sampled at the rising edge of the clock. A system will function correctly and reliably as long as the data are stable around the sampling edge. An SRAM device, on the other hand, is asynchronous. It does not contain a clock signal and its operation is based on the duration and level of the address, data, and control signals. An SRAM device thus is sometimes referred to as asynchronous SRAM.
The timing characteristics of an asynchronous SRAM are quite complex and involve more than two dozen parameters. We concentrate on only a few key parameters that are relevant to our design.
The simplified timing diagrams for two types of read operations are shown in Figure 16.5(a) and (b). The relevant timing parameters are:
The simplified timing diagram for a ve-n-controlled write operation is shown in
Figure 16.6(a). The relevant timing parameters are:
16.3.4 1561LV25616AL SRAM device
The DEl board has an IS61LV25616AL device, which is a 256K-by-16 SRAM module manufactured by Integrated Silicon Solution, Inc. (ISSI). This device has an 18-bit address bus, addr, a 16-bit bidirectional data bus, dq, and five control signals. The data bus is divided into upper and lower bytes, which can be accessed individually. In addition to ce_n, ve_n, and oe_n, it includes two signals to facilitate the byte-oriented configuration:
The extended functional table is shown in Table 16.2.
The values of relevant parameters for the read and write operations are shown in Figures 16.5(c) and 16.6(b).
Our discussion in Part I focuses on the synchronous system, in which the registers are driven by the same clock signals and the input signals are sampled at the rising edge of the clock. A system will function correctly and reliably as long as the data are stable around the sampling edge. An SRAM device, on the other hand, is asynchronous. It does not contain a clock signal and its operation is based on the duration and level of the address, data, and control signals. An SRAM device thus is sometimes referred to as asynchronous SRAM.
The timing characteristics of an asynchronous SRAM are quite complex and involve more than two dozen parameters. We concentrate on only a few key parameters that are relevant to our design.
The simplified timing diagrams for two types of read operations are shown in Figure 16.5(a) and (b). The relevant timing parameters are:
- tRC: read cycle time, the minimal elapsed time between two read operations. It is about the same as tAA for SRAM.
- tAA: address access time, the time required to obtain stable output data after an address change.
- tOHA: output hold time, the time that the output data remains valid after the address changes. This should not be confused with the hold time of an edge-triggered FF, which is a constraint for the d input.
- tDOE: output enable access time, the time required to obtain valid data after
- oe_n is activated.
- tHZOE: output enable to high-Z time, the time for the tristate buffer to enter the high-impedance state after oe_n is deactivated.
- tLZOE: output enable to low-Z time, the time for the tristate buffer to leave the high-impedance state after oe_n is activated. Note that even when the output is no longer in the high-impedance state, the data are still invalid.
Click images to enlarge
Figure 16.5: Timing diagrams and parameters of a read operation.
Click image to enlarge
Figure 16.6 : Timing diagram and parameters of a write operation.
The simplified timing diagram for a ve-n-controlled write operation is shown in
Figure 16.6(a). The relevant timing parameters are:
- tWC: write cycle time, the minimal elapsed time between two write operations.
- tSA: address setup time, the minimal time that the address must be stable before ve_n is activated.
- tHA: address hold time, the minimal time that the address must be stable after ve_n is deactivated.
- tPWE1: ve_n pulse width, the minimal time that ve_n must be asserted.
- tSD: data setup time, the minimal time that data must be stable before the latching edge (the edge in which ve_n moves from 0 to 1).
- tHD: data hold time, the minimal time that data must be stable after the latching edge.
16.3.4 1561LV25616AL SRAM device
The DEl board has an IS61LV25616AL device, which is a 256K-by-16 SRAM module manufactured by Integrated Silicon Solution, Inc. (ISSI). This device has an 18-bit address bus, addr, a 16-bit bidirectional data bus, dq, and five control signals. The data bus is divided into upper and lower bytes, which can be accessed individually. In addition to ce_n, ve_n, and oe_n, it includes two signals to facilitate the byte-oriented configuration:
- lb_n (lower byte enable): disables or enables the lower byte of the data bus
- ub_n (upper byte enable): disables or enables the upper byte of the data bus
The extended functional table is shown in Table 16.2.
Click image to enlarge
Table 16.2: Functional table of IS61LV25616AL control signals
The values of relevant parameters for the read and write operations are shown in Figures 16.5(c) and 16.6(b).
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Evgeni
8/16/2012 2:56 AM EDT
It's amazing how fast the technology is moving. This brand new book is using SOPC in lots of examples. But SOPC is already obsolete; Altera has moved to Qsys, which is quite different SoC interconnect.
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