16.4 SRAM CONTROLLER IP CORE
An SRAM controller is a circuit used to access the external SRAM chip. It generates proper control signals, issues the address, and places and retrieves data according to the device's timing specification.
16.4.1 Avalon interfaces
In the Avalon framework, an SRAM controller can be configured as an SOPC com ponent with an Avalon MM slave interface or Avalon MM tristate slave interface. We use the former to illustrate finer timing issues. In addition to the Avalon MM slave interface, the controller contains an clock input interface for the system clock and a conduit interface to connect the SRAM device's I/O pins.
Avalon MM slave signal mapping
: By examining the specification of the SRAM functional table, we can relate the SRAM's signals with the Avalon MM slave interface signals:
- SRAM's oe_n: read_n
- SRAM's ve_n: vrite_n
- SRAM's ce_n: chipselect_n
- SRAM's ub_n and lb_n: byteenable_n (two bits)
- SRAM's addr: address (18 bits)
- SRAM's dq: readdata (16 bits) and writedata (16 bits)
Note that SRAM's dq
signal (data bus) is bidirectional and thus carries both read and write data. We can use a tristate buffer in the SRAM controller to resolve the situation. The corresponding HDL segment looks like:
Basic timing analysis
: A main task of designing an SRAM controller is to generate a properly timed control signals. In the Avalon framework, the first step is to adjust the timing properties of Avalon MM slave interface's read_n
signals according to the device's specification. We assume that the 50-MHz (i.e., 20-ns) clock signal is used for the Nios II system.
Let us first consider the read operation. In a read cycle, an Avalon MM master issues the address and asserts the read_n
signal at the same time. The SRAM device returns the valid data after 10-ns tAA
. Since the clock period is 20 ns, the Avalon MM master can sample and retrieve the data from readdata
at the rising edge of the next clock. No extra wait state is needed.
The timing diagram of SRAM write operation in Figure 16.6(a) suggests that the write_n
signal should include a setup time to accommodate the SRAM's tsA
requirement and a hold time to accommodate SRAM's tHA
requirements. However, since IS61LV25616AL is a newer chip and all three parameters are zero, it is feasible to issue the address and data and assert write_n
at the same clock cycle. The 20-ns clock period is larger than 10-ns tPWEl
and thus no extra wait state is needed.
Additional timing consideration
: The previous timing analysis is based on a some what ideal scenario. There are several subtle issues in practice. First, the Avalon MM interface is a synchronous protocol and only assures the signals are stable around the clock edge. It does not specify or guarantee the clock-to-output delay or interval of these signals. Thus, the generated signals can be short or may contain glitches. On the other hand, the SRAM timing specification requires the signals to be stable for a specific amount of time (e.g., the 10-ns tpwEl
interval). Second, the propagation delays of signals may vary and the variance can be significant be cause accessing an external device involves various types of I/O propagation delays discussed in Section 16.2.2. The variance can complicate the timing of read since it involves a "round-trip" operation, (i.e., first transmitting address to SRAM and then retrieving data from SRAM). Third, the delay variance may also jeopardize the write operation since it is possible that the data are removed before the deassertion of the we_n
One way to mitigate the problem is to use registers to buffer the incoming and outgoing signals and place these registers within the I/0 buffers. The registered output signals are glitch-free and stable for one clock period and thus resolve the first issue. Utilizing the registers in I/O buffers eliminates the logic-array-to-I/O buffer delay and reduces the main variance in calculating the propagation delays. Due to the relatively large 10-ns slack in read operation (i.e., 20-ns period minus 10-ns tAA
), this approach should resolve the timing difficulty in read operation.
Simultaneous data removal and we_n
deassertion can still pose a problem because of the potential variance of external wiring delays. To be really safe, we can prolong the data and address for one clock cycle by setting the Avalon MM slave interface's holdtime property to 1. This degrades the performance of the write operation from one clock cycle to two clock cycles. An alternative is to use PLL to generate a slightly leading clock signal to drive the we_n
register so that it deasserts slightly before the removal of the data and address signals. However, our test program in Section 16.8 shows that the controller works fine with the original design. It implies that the printed circuit board is designed properly and these features are not needed.
While the registers resolve some timing issues, they introduce latency for data access. In a read operation, it takes one clock cycle to register the outgoing address and oe_n
and another clock cycle to register the incoming data. Thus, an Avalon MM master experiences a latency of two clock cycles. Note that the Avalon MM master can still issue read in every clock cycle and the data are returned in a pipelined fashion. In a write operation, an Avalon MM master issues address, data, and write_n
in the original way. However, because of the buffering registers, the actual SRAM write is delayed by one clock cycle.
16.4.2 Controller circuit
The SRAM controller just consists of registers for the outgoing and incoming signals and a tristate buffer for the bidirectional data bus. Its code is shown in Listing 16.1:
Click image to enlarge
Listing 16.1 SRAM Controller
During synthesis, we can set the Fast Input Register and Fast Output Register options in Quartus to ensure that the registers are placed in I/O buffers. However, software usually can detect the off-chip signals and perform this task automatically.
16.4.3 SOPC component creation
With the HDL file, we can follow the procedure outlined in Section 15.5.4 and create a component in SOPC Builder. The component consists an Avalon MM slave interface (named cpu_ctrl
), a clock interface (named clock_reset
), and a conduit interface for the SRAM signals (named ctrL.sram
). Note that the active-low version of the control signals (i.e., with the _n
suffix) should be used. The complete signal mapping is shown in Figure 16.7.
The Avalon MM slave interface needs to be configured to match the timing characteristics of the SRAM controller. Both Read Wait
and Write Wait
fields should be 0 and the Read latency
field should be 2 to accommodate the two-clock delay introduced by the input and output registers. Furthermore, we need to expand the Deprecated
segment and check the Memory device
box to indicate that the interface is a general-purpose memory module. The finished screen shot is shown in Figure 16.8.
Click image to enlarge
Figure 16.7: Signal mapping of SRAM controller.
In part 2, we will review DRAM and SDRAM.
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