Book excerpt: SRAM and SDRAM controllers for FPGAs, part 2

Editor's note: This excerpt from Embedded SOPC Design with Nios II Processor and Verilog Examples by Pong P. Chu appears courtesy of the editors at John Wiley & Sons Inc. In part 1, we reviewed SRAM, with a particular focus on timing and programming the control. In part two, we will do a similar review of SDRAM. Please note, where appropriate, the examples use Altera’s SOPC Builder tool. Although SOPC Builder is in use by developers around the globe and supported by Altera, the company also has a newer tool called Qsys that does everything SOPC Builder does and more.

16.5 OVERVIEW OF DRAM
Dynamic random access memory (DRAM) stores a bit of data in a capacitor within an integrated circuit. Because of the charge leakage, the memory cell needs to be refreshed periodically. A DRAM cell is very simple and thus a DRAM chip can reach very high density. It is the "main memory" used in today's computer system.

16.5.1 DRAM cell
The basic organization of a DRAM cell is shown on the top right corner of Figure 16.9. The data bit is stored in the capacitor. Its voltage level, which can be close to 0 V (ground) or V_DD (supplied voltage), indicates whether the bit is 0 or The pass transistor functions like a switch and can be turned on or off by the w signal.




The procedure to write a value to a DRAM cell is:

1. Activate word line to turn on the pass transistor.
2. Set bit line 0 V or V_DD to store 0 or 1.
3. Deactivate word line to turn off the pass transistor.

The procedure to read a bit from a DRAM cell is:

1. Precharge bit line to V_DD/2
2. Activate word line to turn on the pass transistor.
3. Use a sense amplifier to detect the voltage swing.
4. Restore (i.e., rewrite) the data back to the capacitor cell (since the original charge content has been destroyed).
5. Deactivate word line to turn off the pass transistor.

Note that the precharge and restoration steps are needed to accommodate the capacitive storage. In addition, since charges in the capacitor leak gradually, its data must be refreshed (i.e., read and then written back) periodically.

16.5.2    Basic DRAM organization
The basic layout of a DRAM chip is similar to that of an SRAM chip. The con­ceptual diagram of a 256-by-1 DRAM is shown in Figure 16.9. The DRAM cells are arranged as a 16-by-16-array and two-dimensional decoding is used to access the designated cell. However, the DRAM addressing scheme is different. The row address is issued first and stored into a latch (i.e., row address latch) and then the column address issued afterward. This scheme reduces the address I/O pins by half. Note that the width of the addr signal is only four bits, half of the size of the SRAM chip. Two additional control signals, ras_n (row address strobe) and cas_n (column address strobe), are used to indicate the type and validity of the addr bus.

1. The basic procedure to read a bit is listed below. We assume that the bit lines have been already precharged.
2. The external controller places the row value on addr.
3. The DRAM stores the address in a row address latch and the row decoder enables a row. The entire row of data is retrieved and stored in a data latch.
4. The external controller places the column value on addr.
5. The DRAM stores the address in a column address latch and the column multiplexer routes the selected data bit to data bus, dq. The retrieved data are also restored back to the original row.
6. The DRAM precharges the bit lines for the next operation.

The write procedure is identical except for step 4. During a write operation, the column decoder enables the selected bit in data latch and the input value from dq is written to that bit. The data latch with the updated bit is then written back to the original row, effectively writing that bit to the cell array.