Book excerpt: SRAM and SDRAM controllers for FPGAs, part 2

16.5.3 DRAM timing
The DRAM does not contain a clock signal and its operation is based on the duration and level of the address, data, and control signals. Because of address time multiplexing and the need of precharging and restoration, DRAM timing is very involved. The simplified timing diagrams of read, write, and refreshing are shown in Figure 16.10. A typical read operation is shown in Figure 16.10(a). The external controller first places the row address on addr and then activates ras_n (i.e., makes it 0). The DRAM latches the address at the falling edge and reads the designated row. After an interval of t_RCD, the row data are stored to the data latch, the controller places the column address on addr and then activates cas_n. The DRAM latches the address at the falling edge and the column multiplexer routes the selected bit to dq. The controller then can deactivate cas_n and remove the data from dq and deactivate ras_n after the row data are restored. After the restoration, DRAM precharges the bit lines for next access. After precharging completes, the controller can start the next access.



The key timing parameters are:

• t_RC: read cycle time, the minimal elapsed time between two read operations.
• t_RAS:  ras_n pulse width, the time interval that ras_n must be asserted.
• t_CAS: cas_n pulse width, the time interval that cas_n must be asserted.
• t_RCD: ras_n to cas_n delay time, the minimal delay between the assertion of ras_n and the assertion of cas_n. It represents the time to retrieve data from a row.
• t_CAC:  cas_n access time, time required to obtain stable output data after cas_n assertion.
• t_RP: row precharge time, time required to precharge a row for another access.

A typical write operation is shown in Figure 16.10(b). The ras_n and cas_n assertions and precharge interval are similar but we_n is activated to write data. In addition to the read and write cycles, a DRAM chip also includes a refresh cycle, as shown in Figure 16.10(c). In this cycle, a row of data is read and then stored back. The external controller usually uses a counter and a timer to keep track of the row number and launch refresh cycles periodically.

Accessing a data item in DRAM requires to read and restore an entire row and to precharge all bit lines. These operations are time consuming and the speed of DRAM is thus relatively slow. One way to improve the performance is to allow multiple column accesses each time a row is retrieved, as in page-mode or burst-mode operation.




16.6  OVERVIEW OF SDRAM
The DRAM timing is very involved and its operation is asynchronous. A signal must be stable for a specific interval of time, not just around a clock edge. To simplify the controller design, modern devices usually include a synchronous control circuit wrapped around the DRAM. The circuit samples the address, data, and control signals at the clock edges and then generates the needed DRAM signals. This type of device is known as SDRAM (synchronous DRAM).

16.6.1  Basic SDRAM organization
The conceptual SDRAM diagram is shown in Figure 16.11. The major "synchronous wrapping circuit" includes a clock generator, registers (blocks with clock input triangle) for the data, address, and commands, and a control circuit that generates DRAM control signals. The data, address, and command signals are sampled at the rising edge of the clk signal and the memory operation can be performed in a pipelined fashion. The device also includes the dqm_n (for "dq mask") signal to mask or enable the data access.

Current SDRAM devices utilize multiple banks, each with its own row decoder and column circuitry, to have several accesses operated in parallel and thus increase overall throughput. The ba signal is used to select a bank.

SDRAM is more versatile than the previous DRAM or SRAM. Various parameters, such as the burst length and burst type (sequential or interleaved), can be adjusted as needed and programmed into the mode register. It can perform a concurrent auto precharge and includes a refresh counter that automatically tracks and increments the refreshing row address.

The SDRAM device keeps the original names of cs_n, ras_n, cas_n, and we_n but groups them together as a 4-bit command. The commands are listed in Table 16.3.