Design Article
Book excerpt: SRAM and SDRAM controllers for FPGAs, part 2
Pong Chu
8/27/2012 12:51 PM EDT
16.6.2 SDRAM timing
Because of the modes and options, SDRAM timing covers many different scenarios. We illustrate the basic concepts by a simple read operation and a simple write operation, in which the burst length is set to 1, the CAS latency is set to 2, and the auto precharge is disabled. The timing diagram of a read operation is shown in Figure 16.12(a). Note that the command and address only need to be stable around the rising edge of the clock.
The basic sequence is:
The key timing parameters are:
Note that the CAS latency is specified in terms of clock cycles. It is usually 2 or 3 and is programmed into the mode register in advance. All other parameters are represented in terms of nanoseconds. While designing the controller, we need to translates a time interval to a proper multiple of clock periods. For example, if tRCD is 50 ns and the clock period is 20 ns, the controller must wait at least 3 clock cycles (i.e., 60 ns) before issuing a read command.
The timing diagram of a write operation is shown in Figure 16.12(b). Its basic sequence is:
There is one new timing parameter:
16.7 SDRAM CONTROLLER AND PLL
16.7.1 Basic SDRAM controller
An SDRAM controller accepts a request from the main system (such as an AvalonÂMM master or a processor) and generates proper SDRAM control signals. It consists of buffers, a timer that issues refreshing ticks, and an FSM that follows the SDRAM timing specification and generates properly sequenced SDRAM commands. The sketch of the FSM state diagram is shown in Figure 16.13. When the power is first applied, the FSM goes through the SDRAM startup process, which consists of a mandatory wait period and several refresh cycles, and then moves to the idle state. Four possible actions can be taken. The main system can issue a request to set the mode register, to read data from SDRAM, or to write data to SDRAM and the timer can trigger the controller to initiate a refresh cycle. The FSM examines the request and branches to the designated path and generates the SDRAM command sequence accordingly.
Because of many possible modes and options of SDRAM, designing a comprehensive and robust SDRAM controller is an involved and tedious task. We use Altera's SDRAM controller IP core for our purposes.
Because of the modes and options, SDRAM timing covers many different scenarios. We illustrate the basic concepts by a simple read operation and a simple write operation, in which the burst length is set to 1, the CAS latency is set to 2, and the auto precharge is disabled. The timing diagram of a read operation is shown in Figure 16.12(a). Note that the command and address only need to be stable around the rising edge of the clock.
Click image to enlarge.
Figure 16.12: Timing diagrams of SDRAM operations.
The basic sequence is:
- At t0, the SDRAM controller issues an activate command and places the row address on addr to initiate the operation. The SDRAM activates the row, retrieves the entire row of data, and stores it to the data latch.
- At t2, the SDRAM controller issues a read command and places the column
- address on addr. The SDRAM enables the column multiplexer to route the selected data to output.
- At t4, the data becomes available in dq and the SDRAM controller retrieves data.
- At t5, the SDRAM controller issues a precharge command.
- At t7, the precharge operation is completed and the SDRAM controller can initiate a new operation at this point.
The key timing parameters are:
- tAC: access time from the clock edge, time required to obtain stable output data after the rising edge of clock.
- CAS latency: cas_n to output data delay, the delay, in terms of number of clock cycles, between the assertion of a read command and the availability of output data.
- tRAS: ras_n pulse width, time interval that ras_n must be asserted.
- tRCD: row to column command delay time, the minimal delay between the assertion of an activate command (i.e., activate a row) and the assertion of a read or write command (i.e., activate a column).
- tRP: precharge command period, time required to complete precharge operation after a precharge command is issued.
Note that the CAS latency is specified in terms of clock cycles. It is usually 2 or 3 and is programmed into the mode register in advance. All other parameters are represented in terms of nanoseconds. While designing the controller, we need to translates a time interval to a proper multiple of clock periods. For example, if tRCD is 50 ns and the clock period is 20 ns, the controller must wait at least 3 clock cycles (i.e., 60 ns) before issuing a read command.
The timing diagram of a write operation is shown in Figure 16.12(b). Its basic sequence is:
- At t0, the SDRAM controller issues an activate command and places the row address on addr to initiate the operation. The SDRAM activates the row, retrieves the entire row of data, and stores it to the data latch.
- At t2, the SDRAM controller issues a write command, places the column address on addr, and places data on the dq bus. The SDRAM retrieves the data, enables the column decoder, writes the selected locations in the data latch, and then writes the entire row of data back to the designated row.
- At t5, the row has been updated and the SDRAM controller issues a precharge command.
- At t7, the precharge operation is completed and the SDRAM controller can initiate a new operation at this point.
There is one new timing parameter:
- tWR: write recovery time, the time interval required between the end of the write data burst and the start of a precharge command.
16.7 SDRAM CONTROLLER AND PLL
16.7.1 Basic SDRAM controller
An SDRAM controller accepts a request from the main system (such as an AvalonÂMM master or a processor) and generates proper SDRAM control signals. It consists of buffers, a timer that issues refreshing ticks, and an FSM that follows the SDRAM timing specification and generates properly sequenced SDRAM commands. The sketch of the FSM state diagram is shown in Figure 16.13. When the power is first applied, the FSM goes through the SDRAM startup process, which consists of a mandatory wait period and several refresh cycles, and then moves to the idle state. Four possible actions can be taken. The main system can issue a request to set the mode register, to read data from SDRAM, or to write data to SDRAM and the timer can trigger the controller to initiate a refresh cycle. The FSM examines the request and branches to the designated path and generates the SDRAM command sequence accordingly.
Figure 16.13: Simplified FSM state diagram of an SDRAM controller.
Because of many possible modes and options of SDRAM, designing a comprehensive and robust SDRAM controller is an involved and tedious task. We use Altera's SDRAM controller IP core for our purposes.
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