Book excerpt: SRAM and SDRAM controllers for FPGAs, part 2

16.7.2 SDRAM controller IP core
Most of today's SDARM devices conform to the standard set by the JEDEC Solid­ State Technology Association. Although the bus width, capacity, and speed differ, the devices utilize similar interfaces, commands, and protocols. It is possible to construct a basic SDRAM controller "skeleton" and then adjust it to match to the system clock speed and specification of a specific SDRAM device. This is the approach used by Altera's SDRAM controller IP core.

An SDRAM controller IP core can be instantiated in SOPC Builder. The process basically requires us to consult the data sheet of a given device and determine the values of the relevant parameters. The timing parameters of IS42Sl6400 can be found in the DEl board's accompanying data sheets. The steps of instantiating an SDRAM controller core are:

1.    In SOPC Builder, select the System Contents tab.
2.    In Component Library panel, expand the Memories and Memory Controllers category and then the SDRAM category and then select SDRAM Controller. The SDRAM Controller subwindow appears. It is in Memory Profile tab page as a default, as shown on the left of Figure 16.14.
3.    In the Presets field, select Custom since there is no pre-configured setting for the IS42Sl6400 device.
4.    Enter the following for IS42Sl6400:

• Bits: 16
• Chip select: 1
• Banks: 4
• Row: 12
• Column: 8

The completed page is shown on the left of Figure 16.14.
5.    Select the Timing tab page to enter relevant timing parameters. The page is shown on the right of Figure 16.14.
6.    Enter the following for the DEl board's SDRAM:

• CAS latency cycles: 3
• Initialization refresh cycles: 8
• Issue one refresh command every: 15.625 us
• Delay after power up, before initialization: 200 us
• Duration of refresh command (Lrfc): 70 ns
• Duration of precharge command (Lrp): 20 ns
• ACTIVE to READ or WRITE delay (Lrcd): 20 ns
• access time (t..ac): 6 ns
• Write recovery time (Lwr, no auto precharge): 14 ns

The completed page is shown on the right of Figure 16.14.
7.    Click finish to complete the process.





16.7.3  SOPC PLL IP core
In a synchronous transaction, the relevant signals must be valid for a small window of time, during which the clock signal must toggle to capture the correct values. This condition translates to a time constraint on the maximal operating clock rate, as discussed in Section 5. The analysis can be applied to a system within the FPGA chip since the internal clock skew is small. However, accessing SDRAM involves additional issues. First, since the SDRAM controller and SDRAM reside on two separate devices, the timing parameters, such as clock-to-q delay, setup time, and hold time, are not identical. Second, as discussed in Section 16.2.2, off-chip access introduces additional delays, and has a significant impact on the controller's clock-to-output time. Finally, clock skew may also exist because the rising edge may not be able to arrive at the SDRAM controller (within the FPGA chip) and the SDRAM device at the same time.

On the DEl board, the clock signal of SDRAM is connected to an output pin of the FPGA device. We can connect this pin directly to the external 50-MHz clock, as shown in Figure 16.15(a). This clocking scheme does not work reliably because of the timing issues. One way to mitigate the problem is to adjust the phase between the controller's clock signal and the SDRAM's clock signal. The basic idea is to determine a window of time, in which the data, address, and control signals are valid at the SDRAM pins, and align the clock's sampling edge in the middle of the window. The exact boundaries of the window depend on SDRAM device's input hold time, setup time, and output hold time, FPGA register's hold time and setup time, the controller's clock-to-output delay, and clock skew. A detailed analysis procedure can be found in the reference of the bibliographic section. DEl documentation suggests to use a -3 ns shift for the SDRAM clock (i.e., the rising edge of the SDRAM clock is ahead of the rising edge of the controller by 3 ns).



The required SDRAM clock adjustment can be done by using FPGA's internal PLL circuit. The improved clocking scheme is shown in Figure 16.15(b). The external 50-MHz clock is fed to the PLL, which generates a clk_sys clock to drive the FPGA's internal system and a clk_sdram clock, which leads by 3 ns, to drive the external SDRAM device. Using PLL output (i.e., clk_sys) to drive the FPGA's internal logic can reduce the clock skew within the FPGA. Furthermore, we can adjust the system's clock frequency with the same 50-MHz external oscillator.

The PLL circuit can be treated as an SOPC Builder component and integrated into a Nios II system or instantiated as a Quartus megafunction module. We use the former for our system. The steps of instantiating a PLL core in SOPC Builder are:

1. In SOPC Builder, select the System Contents tab.
2. In Component Library panel, expand PLL category and then select Avalon ALTPLL. The MegaWizard Plug-In Manage window appears.
3. The window should display the General/Modes sub-page of the Parameter Setting tab page. Enter 50.0 MHz in the What is the frequency of the inclock0 input? since the external 50-MHz oscillator is used for the PLL input.
4. Select the Output Clocks tab page. There are three sub-pages, labeled clk c0,clk cl, and clk c2, which represent three possible output clock signals discussed in Figure 16.The tab page should display the clk c0 sub-page. Its screen capture is shown in Figure 16.16.
5. Check the Use this clock box to activate this clock. Keep the default values for the field. Since both Clock multiplication factor and Clock division factor fields are 1, the clock frequency remains 50 MHz. This clock output is used for the FPGA internal system clock, clk_sym.
6. Select the clk c1 sub-page to configure the second clock. Check the Use this clock box to activate this clock. Enter -3 ns in the Clock phase shift field. This clock output is 50 MHz but with a -3 ns phase shift. It is used to drive the SDRAM device's clock, clk_sdram.
7. Click the Finish button to save the configuration and close the MegaWizard Plug-In Manage window.

Part 3 of this excerpt reviews methodology for testing memory.


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