Design Article
Book excerpt: SRAM and SDRAM controllers for FPGAs, part 3
8/31/2012 10:26 AM EDT
16.10 SUGGESTED EXPERIMENTS
16.10.1 SRAM controller without I/O register
The SRAM controller designed in Section 16.4 includes registers to buffer all off-chip signals. Redesign the controller by removing all registers and modify the Avalon MM slave interface as needed. Resynthesize the circuit, run the testing program, and examine the error rate.
16.10.2 SRAM controller speed test
We can change the system clock rate by adjusting the parameters of the PLL mod ule. Gradually increase the system clock rate from 50 MHz to the maximal allowable clock rate, which can be found in the report of Quartus's Classic Timing Analysis tool. Resynthesize the circuit, run the testing program, and examine the error rate. Note that the output clock frequency of Cyclone II PLL cannot be modified dynamically and thus the system must be resynthesized repeatedly. If a different board is used and the board contains a newer device, a Megafunction known as ALTPLLRECONFIG can be included to facilitate real-time PLL reconfiguration.
16.10.3 SRAM controller with Avalon MM tristate interface
Redesign the SRAM controller using the Avalon MM tristate interface. Resynthesize the circuit, run the testing program, and verify its operation.
16.10.4 SDRAM controller clock skew test
For the SDRAM controller, we can change the phase of the SDRAM clock (i.e., the clk_sdram clock) by adjusting the parameters of the PLL module. Change the phase from -10 ns to +10 ns at 1-ns increments. For each phase, resynthesize the circuit, run the testing program, and examine the error rate.
16.10.5 Memory performance comparison
The HAL platform provides a time stamp utility. It can be used to keep track of the execution time of a program segment. Its use is discussed in Section 21.4. Reconstruct the testing system to include a timer module for time stamping. To compare the performance of three memory modules, develop a testing program that reads 10,000 words from the embedded on-chip memory, from SRAM, and from SDRAM separately and records the execution times. Repeat the procedure for the write operation.
16.10.6 Effect of cache memory
The HAL platform provides a time stamp utility. It can be used to keep track of the execution time of a program segment. Its use is discussed in Section 21.4. Reconstruct the testing system with a "performance" core (i.e., Nios II/f), which contains a data cache, and with a timer module for time stamping. The data cache is used in normal data accesses, such as those in the C program, but can be bypassed by using IORD() and IOWR() functions. Develop a testing program to perform 10,000 data accesses using the cache and 10,000 data accesses without using cache. Observe the effect on data cache. Note that the access pattern can have a significant impact on the hit ratio of the cache and thus effect the average access time.
16.10.7 SDRAM controller from scratch
Instead of using the SOPC Builder's SDRAM controller IP core, design the SDRAM controller from scratch and verify its operation.
Listing 16.5 chu_main_ram_test.c
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16.10.1 SRAM controller without I/O register
The SRAM controller designed in Section 16.4 includes registers to buffer all off-chip signals. Redesign the controller by removing all registers and modify the Avalon MM slave interface as needed. Resynthesize the circuit, run the testing program, and examine the error rate.
16.10.2 SRAM controller speed test
We can change the system clock rate by adjusting the parameters of the PLL mod ule. Gradually increase the system clock rate from 50 MHz to the maximal allowable clock rate, which can be found in the report of Quartus's Classic Timing Analysis tool. Resynthesize the circuit, run the testing program, and examine the error rate. Note that the output clock frequency of Cyclone II PLL cannot be modified dynamically and thus the system must be resynthesized repeatedly. If a different board is used and the board contains a newer device, a Megafunction known as ALTPLLRECONFIG can be included to facilitate real-time PLL reconfiguration.
16.10.3 SRAM controller with Avalon MM tristate interface
Redesign the SRAM controller using the Avalon MM tristate interface. Resynthesize the circuit, run the testing program, and verify its operation.
16.10.4 SDRAM controller clock skew test
For the SDRAM controller, we can change the phase of the SDRAM clock (i.e., the clk_sdram clock) by adjusting the parameters of the PLL module. Change the phase from -10 ns to +10 ns at 1-ns increments. For each phase, resynthesize the circuit, run the testing program, and examine the error rate.
16.10.5 Memory performance comparison
The HAL platform provides a time stamp utility. It can be used to keep track of the execution time of a program segment. Its use is discussed in Section 21.4. Reconstruct the testing system to include a timer module for time stamping. To compare the performance of three memory modules, develop a testing program that reads 10,000 words from the embedded on-chip memory, from SRAM, and from SDRAM separately and records the execution times. Repeat the procedure for the write operation.
16.10.6 Effect of cache memory
The HAL platform provides a time stamp utility. It can be used to keep track of the execution time of a program segment. Its use is discussed in Section 21.4. Reconstruct the testing system with a "performance" core (i.e., Nios II/f), which contains a data cache, and with a timer module for time stamping. The data cache is used in normal data accesses, such as those in the C program, but can be bypassed by using IORD() and IOWR() functions. Develop a testing program to perform 10,000 data accesses using the cache and 10,000 data accesses without using cache. Observe the effect on data cache. Note that the access pattern can have a significant impact on the hit ratio of the cache and thus effect the average access time.
16.10.7 SDRAM controller from scratch
Instead of using the SOPC Builder's SDRAM controller IP core, design the SDRAM controller from scratch and verify its operation.
Listing 16.5 chu_main_ram_test.c
Click image to enlarge.
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