Design Article
Intel's 22-nm process gives MOSFET switch a facelift
Arabinda Das and Alexandre Dorofeev, Senior Technology Analysts, UBM TechInsights
9/6/2012 3:36 PM EDT
Consumer demand for higher performance and lower power has long been the driving force for CMOS technology. The continuous scaling of devices has advanced development of new materials, increased packaging density and added new functionality to the devices that incorporate these design changes.
Scaling involves the shrinkage of all dimensions of a MOSFET, the remarkable switch that allows current to flow in a channel when activated by a gate, then stopping all current flow when the gate is inactivate.
The MOSFET switch has been the cornerstone of many developments in microelectronics. As scaling continues beyond the 30-nm node, however, it has become increasingly difficult to maintain gate control over the channel. This phenomenon, known as short channel effects (SCE), includes all the negative influences associated with device miniaturization, like threshold voltage dependence on channel length. Over the years, IC manufacturers have employed three main approaches to mitigate SCE: source drain engineering, channel engineering and gate stack engineering.
For advanced technology nodes, all three approaches are combined. The Intel 22-nm processor, currently in mass production, is an industry first. UBM TechInsights had the opportunity to analyze the structure and electrical characteristics of this device.
The Intel CORE i5-3550 processor is a quad-core device, codenamed “Ivy Bridge”, fabricated with Intel’s 22 nm process technology and featuring Tri-Gate transistors. Traditional 2-D planar MOS transistors have been replaced with gates that straddle narrow silicon fins rising vertically from the silicon substrate. A thin, high-k dielectric separates the silicon fin from the metal gate on each of the three sides of the fin—one on each side and one across the top—rather than just a top electrode, as is the case with the 2-D planar transistor. Control of the current from the source side of the fin to its drain side is accomplished by a gate on each of the three sides of the fin (hence, “Tri-Gate”) (see figure below).
Figure: SEM tilted view of Intel's 22-nm Tri-Gate device (click on image to enlarge).
Scaling involves the shrinkage of all dimensions of a MOSFET, the remarkable switch that allows current to flow in a channel when activated by a gate, then stopping all current flow when the gate is inactivate.
The MOSFET switch has been the cornerstone of many developments in microelectronics. As scaling continues beyond the 30-nm node, however, it has become increasingly difficult to maintain gate control over the channel. This phenomenon, known as short channel effects (SCE), includes all the negative influences associated with device miniaturization, like threshold voltage dependence on channel length. Over the years, IC manufacturers have employed three main approaches to mitigate SCE: source drain engineering, channel engineering and gate stack engineering.
For advanced technology nodes, all three approaches are combined. The Intel 22-nm processor, currently in mass production, is an industry first. UBM TechInsights had the opportunity to analyze the structure and electrical characteristics of this device.
The Intel CORE i5-3550 processor is a quad-core device, codenamed “Ivy Bridge”, fabricated with Intel’s 22 nm process technology and featuring Tri-Gate transistors. Traditional 2-D planar MOS transistors have been replaced with gates that straddle narrow silicon fins rising vertically from the silicon substrate. A thin, high-k dielectric separates the silicon fin from the metal gate on each of the three sides of the fin—one on each side and one across the top—rather than just a top electrode, as is the case with the 2-D planar transistor. Control of the current from the source side of the fin to its drain side is accomplished by a gate on each of the three sides of the fin (hence, “Tri-Gate”) (see figure below).
Figure: SEM tilted view of Intel's 22-nm Tri-Gate device (click on image to enlarge).
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BHD
9/7/2012 2:04 PM EDT
E-SiC for NMOS strain? Lots of R&D references but in high-volume that's a first as well!
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AD2010
9/7/2012 3:42 PM EDT
The article says Si:C, which implies Si doped with carbon and not SiC (silicon carbide).
Alex and Arabinda
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BHD
9/10/2012 10:48 AM EDT
My typo! I didn't think it would be true silicon carbide.
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Rkuchibhatla
9/14/2012 12:59 PM EDT
Excellent article. How did BEOL scale with the front end?
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VHill79
12/9/2012 2:18 PM EST
We can add as many cores as we like, but eventually we need a breakthrough in technology where size is no longer the issue. When are we going to follow Moore's law on processor frequency? I'm on Typofile: http://typophile.com/user/204946
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resistion
12/9/2012 6:36 PM EST
Glad to see this come out. Thanks.
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