Intel's 22-nm process gives MOSFET switch a facelift
Arabinda Das and Alexandre Dorofeev, Senior Technology Analysts, UBM TechInsights
9/6/2012 3:36 PM EDT
Another challenge facing FinFET device production is process variability as small nanometer differences in the fin structure could make large impacts on device performance. With 193-nm immersion lithography, double patterning and other processing steps, the variation in the fin widths for 22-nm node is about 10 percent as shown in the figure below. These fluctuations could become significant for future fabrication production.
Figure: TEM cross-section perpendicular to the fins and along metal gate (click on image to enlarge).
Although the general concept has been widely researched since the 1990s, only Intel has successfully deployed the first FinFET in volume production. Looking ahead, there are still several options available to drive continued scaling for the future generations: rotating the substrate; forming the FinFETs on silicon-on-insulator or even adopting the surrounding gate architecture.
The greater challenge for advanced technology nodes is not the physical limit of scaling, but rather manufacturability with high yield, which is dependent on low process variability. Over five technology generations (90 nm to 22 nm), Intel has steadily introduced incremental improvements to their source drain, channel and gate-stack engineering processes, but the majority of other process steps have remained unchanged. This incremental improvement process strengthens the existing integration process.
For the 22-nm node, there have been several tradeoffs between performance and integration schemes and multiple process challenges have been overcome. This have yielded improved device performance and given a total face lift to the venerable MOSFET switch.