Design Article
Interfacing QDR-II+ Synchronous SRAM with high-speed FPGAs, part 1
Reshmi Ravindranand Ajay Bharadwaj, Cypress Semiconductor
9/10/2012 3:48 PM EDT
Clocking system for QDR-II+ device
The clocking system for QDR-II+ devices can be divided into input clocks and output clocks. Input clocks are referred to as K and K# clocks. These are provided to the memory by the external controller. These are not differential clocks but are single-ended; however, they are out of phase with each other by 180°. The rising edge of the K clock is used to capture synchronous inputs on the device. All accesses are initiated on the rising edge of the K clock. All synchronous data inputs pass to the input registers and to the core of the memory using the K and K# clocks. The K and K# clocks also pass data from the memory core to the output registers.
The other set of clocks are the output clocks, CQ and CQ#. These clocks help to simplify data capture for high-speed systems. The CQ clock is referenced with respect to the K clock, and CQ# is referenced with respect to the K# clock. The CQ and CQ# clocks are generated by the QDR-II+ device and are called echo clocks. The data on the Q pins are source synchronous with respect to the echo clocks. The user has to shift the echo clock to latch the data. The echo clocks can be phase shifted through board trace delay or by using on-chip circuitry in an FPGA. If circuitry within an FPGA is used to capture the echo clock, then the trace length of the CQ and CQ# clocks must be same as that of the Q pins so that the FPGA can phase shift and capture the data accordingly.
A phase-locked loop (PLL) internal to the chip generates the echo clocks. The advantage of using echo clocks to capture the data is that any jitter that present in the K/K# clocks does not propagate to the output clocks. There is a pin on the QDR-II+ device called the DOFF# pin. This pin is used to switch on or switch off the PLL inside the device. During power up when the DOFF# pin is tied high and 20 µs of stable K/K# clock is provided, then the PLL is locked and the echo clock is generated synchronously to the K/K# clock. When the DOFF# is made low, the PLL is switched off and there is sub-optimal performance of the memory. There is a minimum frequency for the K/K# clock for the PLL to lock; this frequency is provided by the QDR-II+ SRAM manufacturer in the datasheet. Using a frequency below will not lock the PLL, which can affect memory performance.
Locking of the PLL is very critical for the proper operation of the memory device. The following conditions have to be satisfied for the PLL to lock to the correct frequency:
Switching off the PLL of the device is used by the external controllers to train the memory. When the PLL is off, the maximum speed of operation of the system is limited. The FPGA uses this mode to check for the operation of the devices before actual memory operations begin.
Read and write operation
The control signals for the read and write operation are RPS#, WPS#, QVLD and BWS#. RPS# is sampled on the rising edge of the K clock and a read operation is initiated when RPS# is low. A write operation is initiated on the rising edge of the K clock when WPS# is low. BWS# is sampled on the rising edge of the clock and is used to write selectively to one particular byte of the memory. De-selecting BWS# ignores the corresponding byte of data, so that it is not written to the memory. The trace length for address lines, ‘D’ lines, and the control lines should be closely matched. QVLD is an output signal that indicates valid output data. QVLD signal is edge-aligned to the CQ and CQ# lines.
The clocking system for QDR-II+ devices can be divided into input clocks and output clocks. Input clocks are referred to as K and K# clocks. These are provided to the memory by the external controller. These are not differential clocks but are single-ended; however, they are out of phase with each other by 180°. The rising edge of the K clock is used to capture synchronous inputs on the device. All accesses are initiated on the rising edge of the K clock. All synchronous data inputs pass to the input registers and to the core of the memory using the K and K# clocks. The K and K# clocks also pass data from the memory core to the output registers.
The other set of clocks are the output clocks, CQ and CQ#. These clocks help to simplify data capture for high-speed systems. The CQ clock is referenced with respect to the K clock, and CQ# is referenced with respect to the K# clock. The CQ and CQ# clocks are generated by the QDR-II+ device and are called echo clocks. The data on the Q pins are source synchronous with respect to the echo clocks. The user has to shift the echo clock to latch the data. The echo clocks can be phase shifted through board trace delay or by using on-chip circuitry in an FPGA. If circuitry within an FPGA is used to capture the echo clock, then the trace length of the CQ and CQ# clocks must be same as that of the Q pins so that the FPGA can phase shift and capture the data accordingly.
A phase-locked loop (PLL) internal to the chip generates the echo clocks. The advantage of using echo clocks to capture the data is that any jitter that present in the K/K# clocks does not propagate to the output clocks. There is a pin on the QDR-II+ device called the DOFF# pin. This pin is used to switch on or switch off the PLL inside the device. During power up when the DOFF# pin is tied high and 20 µs of stable K/K# clock is provided, then the PLL is locked and the echo clock is generated synchronously to the K/K# clock. When the DOFF# is made low, the PLL is switched off and there is sub-optimal performance of the memory. There is a minimum frequency for the K/K# clock for the PLL to lock; this frequency is provided by the QDR-II+ SRAM manufacturer in the datasheet. Using a frequency below will not lock the PLL, which can affect memory performance.
Locking of the PLL is very critical for the proper operation of the memory device. The following conditions have to be satisfied for the PLL to lock to the correct frequency:
- DOFF# must be high
- Stable K/K# clock has to be provided for a time specified in datasheet (20 µs).
Switching off the PLL of the device is used by the external controllers to train the memory. When the PLL is off, the maximum speed of operation of the system is limited. The FPGA uses this mode to check for the operation of the devices before actual memory operations begin.
Read and write operation
The control signals for the read and write operation are RPS#, WPS#, QVLD and BWS#. RPS# is sampled on the rising edge of the K clock and a read operation is initiated when RPS# is low. A write operation is initiated on the rising edge of the K clock when WPS# is low. BWS# is sampled on the rising edge of the clock and is used to write selectively to one particular byte of the memory. De-selecting BWS# ignores the corresponding byte of data, so that it is not written to the memory. The trace length for address lines, ‘D’ lines, and the control lines should be closely matched. QVLD is an output signal that indicates valid output data. QVLD signal is edge-aligned to the CQ and CQ# lines.
|
|
|
|
|
Navigate to related information