Design Article
Interfacing QDR-II+ Synchronous SRAM with high-speed FPGAs, part 1
Reshmi Ravindranand Ajay Bharadwaj, Cypress Semiconductor
9/10/2012 3:48 PM EDT
Programmable output driver impedance
The QDR-II+ SRAM chip has a pin called the ‘ZQ.’ A resistance has to be connected to this pin to ground. The value of resistance connected adjusts the output driver impedance. The value of resistance must be five times the desired output impedance of the driver; to obtain an output impedance of 50 Ω, for example, the value of ZQ should be equal to 250 Ω.
For high-speed digital devices, terminating the driver impedance with the transmission-line impedance is critical to proper signal integrity for the overall system. The impedance is matched by making the source impedance equal to the load impedance. By changing the value of resistance connected to ZQ pin, the Zsource of the output drivers can be changed accordingly (see figure 2).
Zload must be equal to Zline, which in turn must be equal to Zsource. Zsource is controlled by ZQ, in this case. Zline is the characteristic impedance of the trace that can be matched to be equal to Zsource. The PCB from the memory to the memory controller acts like a transmission line. The Zload should also be matched near the FPGA end. The entire system has to be simulated using IBIS models available for the memory to determine the actual termination values.
Termination of signal lines
Signal integrity is a very important aspect of high-speed digital design and is also very important for interfacing of QDR-II+ SRAM. The drive modes of the inputs and outputs for QDR-II+ SRAMs are high-speed transceiver logic (HSTL). HSTL is a standard interface for digital ICs that calibrates the signal to a reference voltage rather than ground. This enables smaller swings in I/O signal and improves performance by improving signal integrity. HSTL is now becoming a de-facto standard for high-speed digital systems. HSTL requires a reference voltage level that is 50% of maximum voltage. This has to be provided to the Vref pin of the QDR-II+ SRAM.
It is very important to terminate all high-frequency signals because mismatched impedance causes signals to reflect back and forth along the transmission lines, causing ringing and thus impacting the reliability of the system. To eliminate reflection at the source, the impedance of the source must be matched with the transmission line impedance. To eliminate reflection at the load, the impedance of the load must be matched with the impedance of the trace.
Although multiple terminations schemes are available, the most popular and recommended method to terminate the signal is to perform termination at the load with a pull up resistance to Vddq/2 (see figure 4). This scheme requires a separate voltage source that can sink and source currents to match the receiver outputs transfer rates. The value of the pull up resistance can be adjusted to match the load and ensure signal integrity is proper.
All input pins of the QDR-II+ SRAM must be terminated for proper signal integrity. The K/K# clocks must each be terminated separately by having a pull up resistance to Vddq/2. K/K# signals are not fully differential signals and common termination resistance between them is not recommended. The output driver impedance must be matched accordingly to the board impedance for best performance. Certain parts in the QDR-II+ families have on-die termination. These are resistances that are present within the chip and can be programmed according to the termination required. These help in reducing external components and hence conserve board space.
The block diagram below summarizes all the connections required for designing the hardware for QDR-II+ SRAM.
This concludes the hardware details of interfacing QDR-II+ SRAM with FPGA. Part 2 of this article describes the firmware implementation of a QDR controller in popular FPGAs.
About the author
Reshmi Ravindran works as an Applications Engineer at Cypress Semiconductor and supports Cypress’ SRAM products. She holds a Masters in VLSI & Embedded Systems from Model Engineering College, India and a Bachelors in Electronics and Communication from Govt. Rajiv Gandhi Institute of Technology, India.
Ajay Bharadwaj is currently working with Cypress Semiconductors as a Senior Applications Engineer. He holds a Bachelor’s degree in Electronics and Communication engineering. He was a co-founder of a medical device startup. His interests include analog design, digital design and entrepreneurship. He can be reached at ajai@cypress.com.
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The QDR-II+ SRAM chip has a pin called the ‘ZQ.’ A resistance has to be connected to this pin to ground. The value of resistance connected adjusts the output driver impedance. The value of resistance must be five times the desired output impedance of the driver; to obtain an output impedance of 50 Ω, for example, the value of ZQ should be equal to 250 Ω.
For high-speed digital devices, terminating the driver impedance with the transmission-line impedance is critical to proper signal integrity for the overall system. The impedance is matched by making the source impedance equal to the load impedance. By changing the value of resistance connected to ZQ pin, the Zsource of the output drivers can be changed accordingly (see figure 2).
Zload must be equal to Zline, which in turn must be equal to Zsource. Zsource is controlled by ZQ, in this case. Zline is the characteristic impedance of the trace that can be matched to be equal to Zsource. The PCB from the memory to the memory controller acts like a transmission line. The Zload should also be matched near the FPGA end. The entire system has to be simulated using IBIS models available for the memory to determine the actual termination values.
Figure 2: Configuration of output driver impedance.
Termination of signal lines
Signal integrity is a very important aspect of high-speed digital design and is also very important for interfacing of QDR-II+ SRAM. The drive modes of the inputs and outputs for QDR-II+ SRAMs are high-speed transceiver logic (HSTL). HSTL is a standard interface for digital ICs that calibrates the signal to a reference voltage rather than ground. This enables smaller swings in I/O signal and improves performance by improving signal integrity. HSTL is now becoming a de-facto standard for high-speed digital systems. HSTL requires a reference voltage level that is 50% of maximum voltage. This has to be provided to the Vref pin of the QDR-II+ SRAM.
Figure 3: HSTL I/O levels
It is very important to terminate all high-frequency signals because mismatched impedance causes signals to reflect back and forth along the transmission lines, causing ringing and thus impacting the reliability of the system. To eliminate reflection at the source, the impedance of the source must be matched with the transmission line impedance. To eliminate reflection at the load, the impedance of the load must be matched with the impedance of the trace.
Although multiple terminations schemes are available, the most popular and recommended method to terminate the signal is to perform termination at the load with a pull up resistance to Vddq/2 (see figure 4). This scheme requires a separate voltage source that can sink and source currents to match the receiver outputs transfer rates. The value of the pull up resistance can be adjusted to match the load and ensure signal integrity is proper.
Figure 4: Parallel termination at the load.
All input pins of the QDR-II+ SRAM must be terminated for proper signal integrity. The K/K# clocks must each be terminated separately by having a pull up resistance to Vddq/2. K/K# signals are not fully differential signals and common termination resistance between them is not recommended. The output driver impedance must be matched accordingly to the board impedance for best performance. Certain parts in the QDR-II+ families have on-die termination. These are resistances that are present within the chip and can be programmed according to the termination required. These help in reducing external components and hence conserve board space.
The block diagram below summarizes all the connections required for designing the hardware for QDR-II+ SRAM.
Click image to enlarge.
Figure 5: Hardware connections for the interface between QDR-II+ SRAM and FPGA
This concludes the hardware details of interfacing QDR-II+ SRAM with FPGA. Part 2 of this article describes the firmware implementation of a QDR controller in popular FPGAs.
About the author
Reshmi Ravindran works as an Applications Engineer at Cypress Semiconductor and supports Cypress’ SRAM products. She holds a Masters in VLSI & Embedded Systems from Model Engineering College, India and a Bachelors in Electronics and Communication from Govt. Rajiv Gandhi Institute of Technology, India.
Ajay Bharadwaj is currently working with Cypress Semiconductors as a Senior Applications Engineer. He holds a Bachelor’s degree in Electronics and Communication engineering. He was a co-founder of a medical device startup. His interests include analog design, digital design and entrepreneurship. He can be reached at ajai@cypress.com.
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