Clock and data and control signal generation
QDRII+ SRAMs operate on the K and K# input clocks, up to 533 MHZ. The FPGA driver should be able to generate this high frequency clock. It is important that the K and K# clocks be 180º out of phase. The PLLs inside FPGA can be used to generate K, K#, and the other internal clocks needed to generate address, data, and control signals.
K and K# can be either generated as the two phase-shifted outputs of a PLL or as the outputs of double data rate (DDR) I/O macros driven by the common clock output of a PLL. The major concern here is the clocks should have an accurate 180º phase shift irrespective of the operating conditions. In the first method, the clock network of K and K# will be different. So the phase difference between them will be sensitive to loading on each clock network and will be affected if there is significant difference between the fanout of the two clocks.
The ideal method to generate the K clocks is using a PLL clock output to drive the DDR output macros. This will eliminate the effect of difference in clock network fanout on the phase difference. Here, both K and K# are driven from the same clock source and they switch in opposite directions, since the inputs of the two DDR registers are complimentary to each other. Once the K clocks are generated, it is important to assign them to adjacent FPGA pins in order to minimize skew.
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Figure 7: Generating K and K# clocks
QDR devices sample input data on both edges of clock, so the FPGA should be able to provide data on the D bus at double the frequency of the K clock. DDR registers in FPGA I/O banks can be used to achieve this. These registers sample data on both edges of their clock. The register size can be configured to interface with QDRs of any bus width like x9, x18 and x36.
Data has to be driven, ensuring enough set up and hold times with respect to the K and K# clocks. The best method to ensure enough setup and hold time at high speeds is to align the sampling clock edge on the center of data. This can be achieved by having two separate internal clocks to generate the data and QDR clocks. The PLL generates two master internal clocks, C0 and ‘C0_90.’ ‘C0_90’ is the 90º delayed version of C0 and is further used to generate the K and K# clocks. C0 is used to drive data out of the DDR registers on both edges. Since C0 is 90º ahead of C0_90, data will come 90º ahead of K clocks. This, in effect, makes the K and K# clocks center-aligned with the data to be written into QDR.
Control signals RPS# and WPS# can also be driven in a similar way using C0 clock. One important thing to note is the DDR blocks must have a certain delay. To synchronize the data with the K clocks and other control signals, we need to add the DDR registers in the data path of the K clocks and all other signals coming out of the FPGA. Yes, this utilizes some more FPGA resources, but it ensures the same delay for all signal paths.