State machines for control signals
All the clocks and data from the FPGA to the QDR have been generated. The only thing left is to generate the control signals RPS# and WPS# with the proper timing for read and write operations. This can be achieved through a state machine implementation. A sample state machine to assert the WPS# signal in a write operation for a burst-of-two QDRII+ is shown in Figure 8.
Click image to enlarge.
Figure 8: State machine for asserting the control signals in Write operation.
State machines work on either positive or negative clock edges; however, for QDR we need the signals to be asserted on both clock edges. This can be achieved using two state machines—one switching states on rising edge and the other on falling edge of the master clock C0. There is a flag signal output from the first state machine that controls the switching of the second state machine. This flag will be asserted if an action has to be done in the very next falling edge of C0 clock.
In figure 8, on the assertion of a write request (w=1), the state machine switches from IDLE state to the next state, where it asserts the WPS# signal and enables the signal for first data. The flag signal also gets asserted in this state. Once the flag is set to 1, the second state machine switches to state 2.1 on the falling edge of C0. There, it asserts the enable signals for the address and second data. Since the C0 clock is 90º ahead of the K clock, the first data and WPS signal will be sampled on the K clock rising edge while the second data and address are sampled on the K clock falling edge.
Figure 9 shows a sample state machine for asserting the control signals in a read operation for a QDRII+ of 2.5 cycles latency. Depending on whether the device is of 2 or 2.5 cycles latency, we need to adjust the wait states before latching in the read data. This state machine is similar to the write state machine in that it is a combination of two state machines, one switching on rising edge of C0 and the other switching on falling edge of C0.
Click image to enlarge.
Figure 9: State machine for asserting the control signals in Read operation.
On the assertion of a read request (R=1), the state machine switches from IDLE state to the next state, where it asserts the RPS# signal and the read address. Since we have selected a 2.5 cycles latency QDR device, the state machine has to stay in two wait states for the next two cycles. In the second wait state (state 1.2), the flag signal gets asserted. Once the flag is asserted, the second state machine switches to state 2.2 on the very next falling edge of C0; thus, the overall 2.5 cycle latency is taken care of before reading the data. In state 2.2, the enable signal for capturing the first piece of read data gets asserted. The second piece of data will be read on the very next rising edge of C0 in state 1.4. This is a very basic structure of the read and writes state machines and it needs further optimization.
Read data capture
Because QDR memories operate at very high speeds, valid data will only be available on the data bus(Q) for a very short time. The FPGA should capture data in this small time window. Echo clocks CQ and CQ# generated by QDR device allow easy data capture at the FPGA while reading from the memory. Echo clocks are edge-aligned with the data coming out of the memory and act like a flag to the FPGA indicating valid data.
As we have seen in the write operation, the best way to sample the data is at its center. This can be done by delaying the CQ clock so that it comes at the center of read data and then latching data on its edge. PLL logic, DQ and DQS logic, or IODELAY macro offered by various FPGAs can be used to delay the echo clocks for read data capture. When using a PLL, delay one of the echo clocks by 90º and this output clock can be used to clock in the read data at the DDR-in registers.
The DQS delay logic option in some FPGAs allows the addition of delay between the DQS input clock and the output. The DQS phase-shift circuitry uses a frequency reference for the delay chains in DQS pins to compensate for process, voltage, and temperature (PVT) variations. Connect CQ to DQS, CQ# to DQSn, and read data (Q) to DQ. All the DQ signals will be clocked by the DQS strobe signal. The delayed strobe signal can be used to center-align the DQS signal to DQ read data. The delay should be selected to allow the required setup and hold timings.
The following figure shows the complete block diagram of QDRII+ controller using standard IP blocks.
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Figure 10: QDRII+ memory controller block diagram.
QDR memories have become the de-facto standard in networking applications. FPGA vendors are coming up with IP and tools to make the otherwise challenging job of designing memory controllers easier and more flexible. Most of the latest FPGAs provide more or less the same IPs for memory interfaces, but in different names and different configurable options. One should look for the highest frequency and extent of customization of IP when selecting an FPGA to support future generations of QDR.
About the author
Reshmi Ravindran works as an applications engineer at Cypress Semiconductor and supports Cypress’ SRAM products. She holds a Masters in VLSI & Embedded Systems from Model Engineering College, India and a Bachelors in Electronics and Communication from Govt. Rajiv Gandhi Institute of Technology, India.
Ajay Bharadwaj is currently working with Cypress Semiconductors as a Senior Applications Engineer. He holds a Bachelor’s degree in Electronics and Communication engineering. He was a co-founder of a medical device startup. His interests include analog design, digital design and entrepreneurship. He can be reached at email@example.com
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