PCM data retention and the impact of crystal electrodes (Part 2)

Interpreting the data
Although the actual temperatures have not been measured, nor is it known how close the “set” pulse is to optimum, the “set” pulse widths (times) and temperatures that result from the back-extrapolation an shown in figure 1 are not grossly out of line with expectations. At a first glance, the results of the back-extrapolation would suggest that the seeded-bridge model for the PCM set process that was developed in Part 1 is valid and no other types of crystallization processes, such as electric field or current driven electro-crystallization, are involved or are playing a significant role in the PCM “set” process.

While there are lithographic node differences and a number of structural differences such as volume of material involved, thermal barriers, and confining electrodes, the differences in pulse widths of set time t_s=300 ns for Hynix and t_s=150 ns for Samsung are in broad agreement with what would be expected if the back-extrapolation-based model is valid and higher temperatures for crystallization are required. The actual operating “set” and “reset” pulse widths and currents used for the devices on which this analysis is based are shown as annotations in figure 1.

What then does all of this analysis do to accomplish our main goal, which is to confirm the accuracy of the seeded-bridge model for the PCM “set” step and its link to PCM ETDR data? So far the conclusion is the seeded bridge model will facilitate a PCM design trade-off between: ETDR performance, temperature and set time or set-pulse width. The variable that will link temperature and set time will be the set current. For an optimized set pulse, the slower the crystal growth rates the longer the “set” time. All of which have potential implications with respect to overall PCM memory array performance. As a possible means of further testing the correctness of the assumption of my “seeded-bridge” model for the PCM “set” step and its link to PCM ETDR data, I have used the published crystal growth rates for GST compositions. Kalb [8] provides results for a number of different GST compositions that are particularly useful—they’re representative of “seeded” crystal growth in that they exclude the delay time for the incubation-nucleation step that precedes growth. This data [Kalb, 8] represents what is called heterogeneous growth, in which nucleation sites already exist (i.e. the material is seeded). Experimentally, these might be the side walls of a container or crystallites; in the case of the modern PCM structure, that will predominantly be the crystallized GST electrode.





The three new lines that have been added to figure 1 to form figure 2 have used the Kalb growth rates to calculate the crystallization time for a notional PCM device with a 20-nm gap of amorphous material between upper and lower electrodes. These new lines are for a fully crystallized PCM device based on the seeded-bridge model, using an optimized “set” pulse. For each line, the colored region is where the actual growth rates from Kalb have been used. The calculated results are close to what would be expected and although the actual composition of the Samsung material was not disclosed, there is some degree of correlation between part of the calculated line for Ge₂Sb₂T₅ and the three data points for Samsung results.