Optimizing memory design

Identifying reliable risk assessment
The resulting S-parameter correlation provided me with a high level of confidence that I was accurately modeling the memory channel’s PCBs and packages. Moreover, it provided me with a reliable risk assessment of my challenging memory system that matched closely to real-life measurements when the system was powered on in the lab.
 
Modeling the eight-layer package using method of moments simulation software gave my team confidence in the S-parameter model from DC up to 20 GHz (see figure 4). DC proved to be a critical point in our DDR3 memory channel because we used SSTL15 technology for the bus that swings around 0.75 V.



As the data signals move from the die bumps on the top four layers, they are routed as symmetric striplines (see figure 5). The signals change ground reference plane as they move from these layers through the 800-µm core region to pick up the balls of the package with 15-ground PTHs per byte lane.



My team’s layout designer wanted to drop the number of ground PTHs per byte lane, but this was easier said than done. There were questions that had to be answered first. What was the least number of ground PTHs that could be used to ensure low risk for 1.33-GB/s operation? How far away did the ground PTH need to be from signal transitions? Would any of this matter much to the 1.33-GB/s signals, or were we just overdesigning the memory system? Finally, with three-ground PTHs (see figure 6) instead of 15-ground PTHs per byte lane, what about our cost-reduction effort?



The return path discontinuity told us that the biggest impact was on the near-end cross talk (NEXT) with a 10-dB delta for a three-ground PTH, as opposed to a 30-dB delta for the zero-ground PTH compared to the 15-ground PTH (see figure 7).