VCM as a memory alternative
The four-fold density boost delivered by VCM provides MCU manufacturers a major technology alternative by providing a cost-effective and higher security alternative to all three existing options. Of the three, external serial EEPROM and on-chip shadow SRAM is the easiest to eliminate. By replacing the two, a memory array built on the VCM bit cell greatly reduces the security vulnerability and added supply chain/BOM and interface pins costs of the external memory. At the same time, the VCM array fits into an area comparable to or smaller than the shadow SRAM it replaces at process nodes above 28 nm while providing the shadow SRAM’s execute-in-place functionality and reducing the SRAM’s static power drain.
For MCUs that use ROM for program storage because of its compact silicon density and resulting low cost, and its security benefit of being embedded and unchangeable, the small VCM bit cell size offers a compelling alternative. The VCM bit cell does impose a small price increase over ROM. The design requires one extra non-critical mask and one added N-well implant manufacturing step, which increases manufacturing costs. It also includes additional programming circuitry, which increases silicon area compared to ROM, which has no such requirement.
In return for this extra expense, however, MCU manufacturers and embedded designers gain the ability to program the MCU at test time after the chip is manufactured. This means that one MCU can be configured for an unlimited number of SKUs at no inventory cost. In addition, program upgrades and bug fixes can be performed in the field, eliminating revenue loss caused by waiting for software implementation, silicon manufacturing, and chip and product qualification for a ROM respin.
The VCM bit cell’s capacity opens up alternatives for embedded engineers previously forced to use eFlash with their MCUs simply to achieve a limited number of memory modifications. At the same time, the technology also eliminates the limitations imposed by eFlash. Implemented in standard logic CMOS, the VCM bit cell can be fabricated at any foundry and at any process node from 180 nm to 20 nm and below. This alone eliminates the 30% to 40% price burden of adding flash memory fabrication steps to a standard logic process. Because VCM bit cell does not store data using a floating gate to retain a charge, it is resistant to common non-invasive hacking techniques such as data remanence and glitching.
The problem is that in order for the VCM bit cell to provide a reasonable alternative to eFlash, it must trade its superior bit density to provide programmability through emulation: Instead of overwriting existing cells, designs must use new cells to store the new information. As a result, lifetime varies as a function of the volume of data stored. Using a VCM bit-cell memory array to emulate flash memory is a cost-effective alternative for up to a megabit of storage, provided that a design requires no more than 70 program erase cycles over its lifetime (see figure 3). If the design requires less than a megabit of storage, however, VCM can support a much greater number of program erase cycles.
Click image to enlarge.
Figure 3: VCM (Gusto, Salvo) provides a reduced-footprint alternative to embedded alternative techs like SRAM, ROM, and eFlash.
The fourfold increase in memory density provided by the VCM antifuse memory bit cell makes the technology a good substitute for existing memory subsystems in microcontrollers. By replacing conventional eFlash, ROM, and a combination of external serial EEPROM and on-chip shadow SRAM, microcontrollers can now use a standard MCU platform configured by software to address a wide variety of emerging IoT applications that demand ultra-low power, high security, and low cost.
1. P. Clarke, "ARM CEO East on IoT, platforms," EETimes.com (2012 ).
2. C. Holland, "MCUs: High-end devices flourish," MCU Designline (2011).
3. B. Cole, “The growing challenge of securing embedded systems," Embedded Systems Design (2012 ).
About the author
Linh Hong is VP of sales and marketing at Kilopass responsible for Kilopass’ solutions globally. With 16 years of solid semiconductor industry experience, primarily focused on logic NVM IP, high-speed SERDES IP and broadband communication ASICs, Linh served for three years in various director and management positions in field applications engineering and applications marketing at Kilopass before assuming her current role in April 2009. Prior to joining Kilopass, she was a design consultant and design manager at LSI Logic, where she also served in various design and marketing engineering functions. She began her career as a component engineer at Sun Microsystems. Linh holds a BS degree with honors in physics, and an MSEE degree in electrical engineering, both from University of California, Davis.