Korean memory maker Hynix recently introduced its 30-nm class (3X) DRAM. UBM TechInsights
performed a complete structural analysis of the low power, 2-Gbit DDR3 SDRAM H5TC2G83CFR-H9R.
Surprisingly, the wordline (WL) pitch measured in the bitline (BL) direction was found to be the same as in the previous generation Hynix 44-nm 2-Gbit DDR3 SDRAM
, which was measured to be 88 nm. Usually, the technology node for DRAM is defined as the half-wordline pitch. According to the standard definition, the H5TC2G83CFR-H9R device remains at the same node as the previous generation. However, the unit cell of this new device is 40 percent smaller than that of the 44-nm node device.
As seen in the figure below, the process integration scheme is significantly different: The Hynix 44-nm SDRAM has a WL above the Si substrate level and the array transistor employs the saddle-fin structure; the new Hynix SDRAM has a WL below the substrate surface and uses the buried-wordline (bWL) scheme.
Click on image to enlarge.
Figure 1: Unit cell and wordline (WL) pitch, SEM cross-section, in bitline direction. Hynix 44 nm and Hynix 31 nm both have the same WL pitch (88 nm), which by conventional definition implies that the technology node is 44 nm. Hynix 31-nm device uses a buried wordline line integration scheme and has a smaller unit cell than Hynix 44 nm.