Pitch defines node
Another common definition for technology node is the minimum lithographically implemented feature size. In the early nodes, as seen in the table below
, the shallow trench isolation (STI) pitch, BL pitch, and the WL pitch are all similar. Half of the WL pitch represents the minimum feature size. After the 70-nm node, the STI pitch shrink did not keep pace with the WL pitch shrink until the recessed-channel-array-transistor (RCAT) was introduced by Samsung and later by others. RCAT shrunk the STI pitch in the array. When Samsung introduced its 30-nm class SDRAM K4B2G0846D 2Gbit DDR3
, it used STI pitch to define process node.
The Hynix 30-nm-class SDRAM followed the same trend. Micron is the only major SDRAM manufacturer that still uses the historic definition of half WL pitch to define the technology node. Micron’s 30-nm class SDRAM MT41K512M8RH-125
has a half WL pitch of 31 nm and half STI pitch of 45 nm. Irrespective of what parameter the manufacturer has taken as the minimum feature size, one parameter is common: every new technology node has a smaller SDRAM cell area than the previous generation.
Table 1: Summary of 6 generations of Hynix SDRAM products.
(*STI pitch is measured perpendicular to the active array and its half pitch is used to define the technology node for Hynix’s 30-nm class SDRAM).
The table above indicates that Hynix 3X SDRAM is different compared to previous generations. It is the only memory device that uses half-STI pitch to define the technology node while utilizing a new cell layout. Hynix was the only manufacturer still using 8F2 layout for sub-70nm nodes. The 8F2 layout has two major advantages:
1.The noise immunity is higher and the process complexity is lower due to larger cell size compared to the 6F2 layout.
2. Conversely the 6F2 scheme provides a significant (25 percent) cell area reduction with the same design rule. Micron was the first company to switch to 6F2 with its 95-nm node SDRAM and Samsung introduced 6F2 layout in its 80-nm node SDRAM. Hynix continued using 8F2 layout until the introduction of this device.