Design Article
Hynix DRAM layout, process integration adapt to change
Arabinda Das, UBM TechInsights
12/18/2012 11:00 AM EST
Pitch defines node
Another common definition for technology node is the minimum lithographically implemented feature size. In the early nodes, as seen in the table below, the shallow trench isolation (STI) pitch, BL pitch, and the WL pitch are all similar. Half of the WL pitch represents the minimum feature size. After the 70-nm node, the STI pitch shrink did not keep pace with the WL pitch shrink until the recessed-channel-array-transistor (RCAT) was introduced by Samsung and later by others. RCAT shrunk the STI pitch in the array. When Samsung introduced its 30-nm class SDRAM K4B2G0846D 2Gbit DDR3, it used STI pitch to define process node.
The Hynix 30-nm-class SDRAM followed the same trend. Micron is the only major SDRAM manufacturer that still uses the historic definition of half WL pitch to define the technology node. Micron’s 30-nm class SDRAM MT41K512M8RH-125 has a half WL pitch of 31 nm and half STI pitch of 45 nm. Irrespective of what parameter the manufacturer has taken as the minimum feature size, one parameter is common: every new technology node has a smaller SDRAM cell area than the previous generation.
The table above indicates that Hynix 3X SDRAM is different compared to previous generations. It is the only memory device that uses half-STI pitch to define the technology node while utilizing a new cell layout. Hynix was the only manufacturer still using 8F2 layout for sub-70nm nodes. The 8F2 layout has two major advantages:
1.The noise immunity is higher and the process complexity is lower due to larger cell size compared to the 6F2 layout.
2. Conversely the 6F2 scheme provides a significant (25 percent) cell area reduction with the same design rule. Micron was the first company to switch to 6F2 with its 95-nm node SDRAM and Samsung introduced 6F2 layout in its 80-nm node SDRAM. Hynix continued using 8F2 layout until the introduction of this device.
Next: Saddle-fin transistor
Another common definition for technology node is the minimum lithographically implemented feature size. In the early nodes, as seen in the table below, the shallow trench isolation (STI) pitch, BL pitch, and the WL pitch are all similar. Half of the WL pitch represents the minimum feature size. After the 70-nm node, the STI pitch shrink did not keep pace with the WL pitch shrink until the recessed-channel-array-transistor (RCAT) was introduced by Samsung and later by others. RCAT shrunk the STI pitch in the array. When Samsung introduced its 30-nm class SDRAM K4B2G0846D 2Gbit DDR3, it used STI pitch to define process node.
The Hynix 30-nm-class SDRAM followed the same trend. Micron is the only major SDRAM manufacturer that still uses the historic definition of half WL pitch to define the technology node. Micron’s 30-nm class SDRAM MT41K512M8RH-125 has a half WL pitch of 31 nm and half STI pitch of 45 nm. Irrespective of what parameter the manufacturer has taken as the minimum feature size, one parameter is common: every new technology node has a smaller SDRAM cell area than the previous generation.
Table 1: Summary of 6 generations of Hynix SDRAM products.
(*STI pitch is measured perpendicular to the active array and its half pitch is used to define the technology node for Hynix’s 30-nm class SDRAM).
(*STI pitch is measured perpendicular to the active array and its half pitch is used to define the technology node for Hynix’s 30-nm class SDRAM).
The table above indicates that Hynix 3X SDRAM is different compared to previous generations. It is the only memory device that uses half-STI pitch to define the technology node while utilizing a new cell layout. Hynix was the only manufacturer still using 8F2 layout for sub-70nm nodes. The 8F2 layout has two major advantages:
1.The noise immunity is higher and the process complexity is lower due to larger cell size compared to the 6F2 layout.
2. Conversely the 6F2 scheme provides a significant (25 percent) cell area reduction with the same design rule. Micron was the first company to switch to 6F2 with its 95-nm node SDRAM and Samsung introduced 6F2 layout in its 80-nm node SDRAM. Hynix continued using 8F2 layout until the introduction of this device.
Next: Saddle-fin transistor
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Rkuchibhatla
12/19/2012 2:41 PM EST
Nice work and good analysis. Do you think the bWL architecture can be exended to 2x nm node? I think the cell capacitance is also an issue at 2x nm and higher density requirements may push to look for other memory alternatives beyond 2x node.
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AD2010
12/19/2012 5:05 PM EST
Yes bWl can be extended to 2x node by changing layout to 4F2.
There are some processing issues but 4F2 with bWL is possible.
For increasing cell capacitance, apart from looking at new dielectrics, there are some other tricks like using amorphous layers.
The industry is always looking for other memory alternatives and it will come...
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mifb
12/21/2012 4:00 PM EST
It doesn't make sense to call it a 3xnm node when it is in reality a 4xnm DRAM technology. The reduced cell size would not justify this naming convention, since the competitors Samsung and Micron are using 6F2 designs allready.
What about the IP situation, did Hynix buy the the bWL patents out of the Qimonda bankruptcy assets?
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AD2010
12/23/2012 8:31 AM EST
Micron & Samsung have been using 6F2 layout since many generations. So layout is not an indication of tech-node.
In the early days for logic devices for defining the tech-node gate length was the main parameter then it became metal-1 pitch and the contacted gate pitch but now the most reliable parameter is the 6T-SRAM cell area.
Cell area will emerge as important criteria for DRAM too.
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resistion
1/25/2013 2:05 PM EST
I was intrigued by their 31 nm active area double patterning.
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