Design Article
Hynix DRAM layout, process integration adapt to change
Arabinda Das, UBM TechInsights
12/18/2012 11:00 AM EST
Saddle-fin transistor
At the 44-nm node, Hynix used a saddle-fin transistor as an access device but maintained the old layout of 8F2. The saddle fin scheme is essentially a combination of FinFet and RCAT process-flows. The saddle-fin transistor was designed to decrease storage node write time as well as improve short channel effects with the addition of a partial triple-gate structure. The result is better control over the channel region than the RCAT structure used in Hynix 54-nm SDRAM.
However, it has become increasingly difficult to shrink the cell size using the 8F2 layout. As a result, Hynix eventually adopted the 6F2 layout while also implementing the bWL concept. In the bWL cell, the transistor gates are merged with the metal WL running below the silicon surface level, thus enabling a simple cell structure. Due to a less complex structure, the BL-to-WL capacitive coupling is strongly reduced, resulting in a higher read margin and, subsequently, lower power consumption.
The die is fabricated using a 3x nm CMOS process with stacked capacitor and bWL scheme. Hynix has kept the same WL pitch as that of its previous generation but has reduced the STI spacing by making the active area slanted by 19 degrees from the BL direction as shown in the figure below. The slanted active areas are not continuous but form islands separated by STI. The 6F2 SDRAM unit cell measures 0.131 µm and 0.071 µm along the WL and the BL directions respectively, resulting in a given unit cell area of 0.0093 µm2.
Click on image to enlarge.
Next: Storage-node contacts
At the 44-nm node, Hynix used a saddle-fin transistor as an access device but maintained the old layout of 8F2. The saddle fin scheme is essentially a combination of FinFet and RCAT process-flows. The saddle-fin transistor was designed to decrease storage node write time as well as improve short channel effects with the addition of a partial triple-gate structure. The result is better control over the channel region than the RCAT structure used in Hynix 54-nm SDRAM.
However, it has become increasingly difficult to shrink the cell size using the 8F2 layout. As a result, Hynix eventually adopted the 6F2 layout while also implementing the bWL concept. In the bWL cell, the transistor gates are merged with the metal WL running below the silicon surface level, thus enabling a simple cell structure. Due to a less complex structure, the BL-to-WL capacitive coupling is strongly reduced, resulting in a higher read margin and, subsequently, lower power consumption.
The die is fabricated using a 3x nm CMOS process with stacked capacitor and bWL scheme. Hynix has kept the same WL pitch as that of its previous generation but has reduced the STI spacing by making the active area slanted by 19 degrees from the BL direction as shown in the figure below. The slanted active areas are not continuous but form islands separated by STI. The 6F2 SDRAM unit cell measures 0.131 µm and 0.071 µm along the WL and the BL directions respectively, resulting in a given unit cell area of 0.0093 µm2.
Click on image to enlarge.
Figure 2: SDRAM array, at diffusion level, SEM topographical view of Hynix 44 nm (left) and Hynix 31 nm (right). Active areas of Hynix 31-nm device are slanted and the bitline makes a 19 degree angle with the active area.
Next: Storage-node contacts
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Rkuchibhatla
12/19/2012 2:41 PM EST
Nice work and good analysis. Do you think the bWL architecture can be exended to 2x nm node? I think the cell capacitance is also an issue at 2x nm and higher density requirements may push to look for other memory alternatives beyond 2x node.
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AD2010
12/19/2012 5:05 PM EST
Yes bWl can be extended to 2x node by changing layout to 4F2.
There are some processing issues but 4F2 with bWL is possible.
For increasing cell capacitance, apart from looking at new dielectrics, there are some other tricks like using amorphous layers.
The industry is always looking for other memory alternatives and it will come...
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mifb
12/21/2012 4:00 PM EST
It doesn't make sense to call it a 3xnm node when it is in reality a 4xnm DRAM technology. The reduced cell size would not justify this naming convention, since the competitors Samsung and Micron are using 6F2 designs allready.
What about the IP situation, did Hynix buy the the bWL patents out of the Qimonda bankruptcy assets?
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AD2010
12/23/2012 8:31 AM EST
Micron & Samsung have been using 6F2 layout since many generations. So layout is not an indication of tech-node.
In the early days for logic devices for defining the tech-node gate length was the main parameter then it became metal-1 pitch and the contacted gate pitch but now the most reliable parameter is the 6T-SRAM cell area.
Cell area will emerge as important criteria for DRAM too.
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resistion
1/25/2013 2:05 PM EST
I was intrigued by their 31 nm active area double patterning.
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