Each slanted active area has two storage-node contacts (SNC) and one BL-contact. For slanted active areas, SNCs and BL-contacts are automatically staggered in the BL direction, which implies that in any given BL direction either a row of SNC exists or a row of BL-contacts is found – but not both (as shown in the figure below
). This configuration helps to reduce the cell area and to keep straight bitlines.
Figure 3: SEM cross-sections through storage node contacts and bitline contacts, Bitline direction for SK- Hynix 31 nm SDRAM. The SNC and the BL-contacts are staggered along BL direction due to the slanted active area.
The rest of the Hynix 31-nm device
process is similar to its previous 44-nm node technology.
Even though the capacitor module and the peripheral transistors are identical to the previous generation, the 30-nm-class Hynix SDRAM is still a major step for the company and its viability. Hynix had put considerable R&D effort into saddle-fin technology but has used it once before – for the previous technology node (44 nm). This is not cost effective in terms of production.