Design Article
Hynix DRAM layout, process integration adapt to change
Arabinda Das, UBM TechInsights
12/18/2012 11:00 AM EST
Storage-node contacts
Each slanted active area has two storage-node contacts (SNC) and one BL-contact. For slanted active areas, SNCs and BL-contacts are automatically staggered in the BL direction, which implies that in any given BL direction either a row of SNC exists or a row of BL-contacts is found – but not both (as shown in the figure below). This configuration helps to reduce the cell area and to keep straight bitlines.
Figure 3: SEM cross-sections through storage node contacts and bitline contacts, Bitline direction for SK- Hynix 31 nm SDRAM. The SNC and the BL-contacts are staggered along BL direction due to the slanted active area.
The rest of the Hynix 31-nm device process is similar to its previous 44-nm node technology.
Even though the capacitor module and the peripheral transistors are identical to the previous generation, the 30-nm-class Hynix SDRAM is still a major step for the company and its viability. Hynix had put considerable R&D effort into saddle-fin technology but has used it once before – for the previous technology node (44 nm). This is not cost effective in terms of production.
Next: Smaller cell area
Each slanted active area has two storage-node contacts (SNC) and one BL-contact. For slanted active areas, SNCs and BL-contacts are automatically staggered in the BL direction, which implies that in any given BL direction either a row of SNC exists or a row of BL-contacts is found – but not both (as shown in the figure below). This configuration helps to reduce the cell area and to keep straight bitlines.
Figure 3: SEM cross-sections through storage node contacts and bitline contacts, Bitline direction for SK- Hynix 31 nm SDRAM. The SNC and the BL-contacts are staggered along BL direction due to the slanted active area.
The rest of the Hynix 31-nm device process is similar to its previous 44-nm node technology.
Even though the capacitor module and the peripheral transistors are identical to the previous generation, the 30-nm-class Hynix SDRAM is still a major step for the company and its viability. Hynix had put considerable R&D effort into saddle-fin technology but has used it once before – for the previous technology node (44 nm). This is not cost effective in terms of production.
Next: Smaller cell area
|
|
|
|
|
Navigate to related information
Rkuchibhatla
12/19/2012 2:41 PM EST
Nice work and good analysis. Do you think the bWL architecture can be exended to 2x nm node? I think the cell capacitance is also an issue at 2x nm and higher density requirements may push to look for other memory alternatives beyond 2x node.
Sign in to Reply
AD2010
12/19/2012 5:05 PM EST
Yes bWl can be extended to 2x node by changing layout to 4F2.
There are some processing issues but 4F2 with bWL is possible.
For increasing cell capacitance, apart from looking at new dielectrics, there are some other tricks like using amorphous layers.
The industry is always looking for other memory alternatives and it will come...
Sign in to Reply
mifb
12/21/2012 4:00 PM EST
It doesn't make sense to call it a 3xnm node when it is in reality a 4xnm DRAM technology. The reduced cell size would not justify this naming convention, since the competitors Samsung and Micron are using 6F2 designs allready.
What about the IP situation, did Hynix buy the the bWL patents out of the Qimonda bankruptcy assets?
Sign in to Reply
AD2010
12/23/2012 8:31 AM EST
Micron & Samsung have been using 6F2 layout since many generations. So layout is not an indication of tech-node.
In the early days for logic devices for defining the tech-node gate length was the main parameter then it became metal-1 pitch and the contacted gate pitch but now the most reliable parameter is the 6T-SRAM cell area.
Cell area will emerge as important criteria for DRAM too.
Sign in to Reply
resistion
1/25/2013 2:05 PM EST
I was intrigued by their 31 nm active area double patterning.
Sign in to Reply