Smaller cell area
Moreover, Hynix has also switched over to a 6F2 layout from a 8F2 layout, which it used for at least five generations. In a commodity market with ever-diminishing profits, it is necessary to critically analyze one’s own cherished technology and evaluate if it can be prolonged or adapted to future technologies. Hynix has survived and adoption of the bWL and the new 6F2 layout has given the Hynix 31-nm device a smaller cell area comparable to that of other two major SDRAM manufacturers (Samsung and Micron).
The figure below shows the square root of DRAM cell area versus technology node. For earlier generations, by the given design rule, the cell area of Hynix’s SDRAM device is larger than that of Micron or Samsung. That is because the other two manufacturers chose to utilize the 6F2 layout. This same figure also suggests that for each manufacturer the square root of its SDRAM cell area decreases linearly as a function of technology node.
For future technology nodes, it may be difficult to compare the effect of device geometry scaling and cell array-architecture change, as device makers are trying different ways to reduce the cell area and increase the Mbytes/ cm2. It makes a lot of sense to consider the SDRAM unit cell area as the main parameter to define a technology node.
Figure 4: Square root of unit cell Vs technology node for three major DRAM manufacturers.
UBM Techinsights analyzed recently the 30-nm class SDRAM of Samsung, Hynix, Micron and Elpida. All four manufacturers use different novel process innovations to shrink their respective SDRAM cell area. From this analysis, it is interesting to see the novel approach each DRAM manufacturer takes in developing towards their next process shrink as the highly volatile and competitive DRAM market is taken into consideration with each design.
-- Arabinda Das is a senior analyst at UBM TechInsights.