Design Article
Hynix DRAM layout, process integration adapt to change
Arabinda Das, UBM TechInsights
12/18/2012 11:00 AM EST
Smaller cell area
Moreover, Hynix has also switched over to a 6F2 layout from a 8F2 layout, which it used for at least five generations. In a commodity market with ever-diminishing profits, it is necessary to critically analyze one’s own cherished technology and evaluate if it can be prolonged or adapted to future technologies. Hynix has survived and adoption of the bWL and the new 6F2 layout has given the Hynix 31-nm device a smaller cell area comparable to that of other two major SDRAM manufacturers (Samsung and Micron).
The figure below shows the square root of DRAM cell area versus technology node. For earlier generations, by the given design rule, the cell area of Hynix’s SDRAM device is larger than that of Micron or Samsung. That is because the other two manufacturers chose to utilize the 6F2 layout. This same figure also suggests that for each manufacturer the square root of its SDRAM cell area decreases linearly as a function of technology node.
For future technology nodes, it may be difficult to compare the effect of device geometry scaling and cell array-architecture change, as device makers are trying different ways to reduce the cell area and increase the Mbytes/ cm2. It makes a lot of sense to consider the SDRAM unit cell area as the main parameter to define a technology node.
Figure 4: Square root of unit cell Vs technology node for three major DRAM manufacturers.
UBM Techinsights analyzed recently the 30-nm class SDRAM of Samsung, Hynix, Micron and Elpida. All four manufacturers use different novel process innovations to shrink their respective SDRAM cell area. From this analysis, it is interesting to see the novel approach each DRAM manufacturer takes in developing towards their next process shrink as the highly volatile and competitive DRAM market is taken into consideration with each design.
-- Arabinda Das is a senior analyst at UBM TechInsights.
Moreover, Hynix has also switched over to a 6F2 layout from a 8F2 layout, which it used for at least five generations. In a commodity market with ever-diminishing profits, it is necessary to critically analyze one’s own cherished technology and evaluate if it can be prolonged or adapted to future technologies. Hynix has survived and adoption of the bWL and the new 6F2 layout has given the Hynix 31-nm device a smaller cell area comparable to that of other two major SDRAM manufacturers (Samsung and Micron).
The figure below shows the square root of DRAM cell area versus technology node. For earlier generations, by the given design rule, the cell area of Hynix’s SDRAM device is larger than that of Micron or Samsung. That is because the other two manufacturers chose to utilize the 6F2 layout. This same figure also suggests that for each manufacturer the square root of its SDRAM cell area decreases linearly as a function of technology node.
For future technology nodes, it may be difficult to compare the effect of device geometry scaling and cell array-architecture change, as device makers are trying different ways to reduce the cell area and increase the Mbytes/ cm2. It makes a lot of sense to consider the SDRAM unit cell area as the main parameter to define a technology node.
Figure 4: Square root of unit cell Vs technology node for three major DRAM manufacturers.
UBM Techinsights analyzed recently the 30-nm class SDRAM of Samsung, Hynix, Micron and Elpida. All four manufacturers use different novel process innovations to shrink their respective SDRAM cell area. From this analysis, it is interesting to see the novel approach each DRAM manufacturer takes in developing towards their next process shrink as the highly volatile and competitive DRAM market is taken into consideration with each design.
-- Arabinda Das is a senior analyst at UBM TechInsights.
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Rkuchibhatla
12/19/2012 2:41 PM EST
Nice work and good analysis. Do you think the bWL architecture can be exended to 2x nm node? I think the cell capacitance is also an issue at 2x nm and higher density requirements may push to look for other memory alternatives beyond 2x node.
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AD2010
12/19/2012 5:05 PM EST
Yes bWl can be extended to 2x node by changing layout to 4F2.
There are some processing issues but 4F2 with bWL is possible.
For increasing cell capacitance, apart from looking at new dielectrics, there are some other tricks like using amorphous layers.
The industry is always looking for other memory alternatives and it will come...
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mifb
12/21/2012 4:00 PM EST
It doesn't make sense to call it a 3xnm node when it is in reality a 4xnm DRAM technology. The reduced cell size would not justify this naming convention, since the competitors Samsung and Micron are using 6F2 designs allready.
What about the IP situation, did Hynix buy the the bWL patents out of the Qimonda bankruptcy assets?
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AD2010
12/23/2012 8:31 AM EST
Micron & Samsung have been using 6F2 layout since many generations. So layout is not an indication of tech-node.
In the early days for logic devices for defining the tech-node gate length was the main parameter then it became metal-1 pitch and the contacted gate pitch but now the most reliable parameter is the 6T-SRAM cell area.
Cell area will emerge as important criteria for DRAM too.
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resistion
1/25/2013 2:05 PM EST
I was intrigued by their 31 nm active area double patterning.
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