Everspin turned heads a few weeks ago when it announced that it was sampling a 64-Mb DDR3 spin torque magnetoresistive random access memory
(ST-MRAM), aimed at the SSD market. We got an advance peek at some of the results they presented on the technology at the 2012 International Electron Devices Meeting (IEDM); look for the full paper to post on the Memory Designline later this year.
Figure 1: Alternative materials and careful attention to process control delivered a cell structure that open the way for practical ST-RAM.
Plenty of technologies look promising at the research level but the road to market is blocked by barrier after barrier. Is the technology repeatable? Is it robust enough to operate outside the lab? If so, can it be reliably manufactured? Can it scale up to volume production? And will it be viable in a systems environment? After almost two decades of development, for ST-MRAM, apparently, the answer to all of these questions is yes.
Early on, MRAM was touted as the next great thing in memory. Unlike DRAM, SRAM, and flash memory, MRAM is not based on stored charge but on stable magnetization states of a magnetic tunnel junction (MTJ; see MRAM 101—what you need to know
). The energy barrier to switching states makes the memory nonvolatile; the mechanism by which the state is switched enables unlimited endurance. MRAM promised a faster write speed than flash memory, lower power consumption than SRAM or FRAM, and smaller cell sizes than nearly all of the above. Companies ranging from IBM and Hitachi to Toshiba invested time and money in the technology. Freescale Semiconductor spun out its MRAM effort as Everspin Technologies. Analysts and early proponents predicted that MRAM would own the market.
And time passed.
Initial MRAM implementations used a combination of current run through both a row and a column of an MTJ array to generate a magnetic field that in turn flipped the polarity of the MTJ for a given cell. This consumed a fair amount of power. Worse, because of normal material variation, the devices suffered from half-select disturbs. This is a phenomenon in which bits that share the row or the column of the cell being switched might inadvertently be exposed to a high enough field from just the one axis to be switched unintentionally, causing false writes. Suddenly, two of the value propositions that were supposed to make the technology overcome all competitors disappeared, at the same time as the memory market began shifting away from PCs and toward embedded devices, which are most sensitive to power issues; and enterprise-level data storage, which requires accuracy and reliability above all else. Meanwhile, incumbent memory technologies like DRAM and NAND flash Improved enough to remain competitive.
An improved version of MRAM known as toggle MRAM overcame the problem of half select disturbs, opening the way for commercialization. Indeed, in 2005, Everspin began shipping 4-Mb toggle MRAM chips for applications like write journal or data log functions in RAID disk arrays, battery-free SRAM replacement in enterprise-level SSDs, and instant-on software and firmware storage for a variety of industrial systems; today, they offer devices as large as 16 Mb.
Despite the improvements, toggle MRAM still has key limitations. The write operation consumes a significant amount of current, which places an upper bound on write speed. Indeed, toggle MRAM cannot support DDR3 data rates because the switching current required to achieve the specified bandwidth would drive power consumption above levels the package could tolerate.
Just as significant, the technology runs into problems at high densities. “Toggle MRAM has scalability issues because as you shrink the bit, the write currents don’t shrink proportionally,” says Everspin CEO Phill LoPresti. “In fact, sometimes they stay quite similar.” This behavior limits the length of the conductors carrying the write current, as well as the scaling of the write drivers. The two combine to decrease the area efficiency of the array—the bit size might shrink but the area required for the circuitry remains the same, so that past a certain point circuitry dominates the array. This efficiency drop, along with electromigration of the conductors carrying the write current, present practical minimum bounds to bit size, and maximum bounds to capacity.
Enter ST-MRAM. Instead of flipping the polarity of the MTJs via current-induced localized magnetic fields, ST-MRAM flips the bits directly using spin-polarized current. The reduced switching current and simplified circuitry of ST-MRAM enables it to support the write bandwidth required for DDR3 performance.