Requirements for commercial ST-MRAM
Bringing a sophisticated technology like ST-MRAM to market is non trivial. Today’s applications demand ever higher memory densities, which means shrinking the MTJs. Smaller MTJs provide a secondary scaling benefit, too. An ST-MRAM memory cell consists of an MTJ and a transistor for the read/write operation. The saturation current Id-sat
, for the transistor associated with each cell is proportional to required switching currents (Isw
), which are related to the MTJ area, which scales with the square of the feature size. For a constant threshold switching current density JC
, the MTJ defines the minimum size of transistor that can be used, which directly affects both power consumption and heating.
To guard against accidental overwrites or device failure, the voltage threshold for switching the array (Vsw
) needs to be well separated from both the the critical voltage for switching (VC
) and the tunnel-barrier breakdown voltage (Vbd
). That separation is nominally around 6σ
but because the probability of a failure is a function of the total time which the write voltage is applied, the separation required for a practical device is several times larger.
The smaller the MTJ area A
, the lower Ic
. So far, so good, right? Not necessarily. The energy barrier to switching, Eb
, is roughly proportional to A
. Make the cell too small, and you run the risk of degrading data stability unless you can boost Eb
. Working with an asymmetric bit shape and thicker ferromagnetic layers can modestly increase Eb
, but choosing a material with higher magnetization provides much greater benefit—according to the Everspin team, just a 10% improvement in saturation magnetization can bump Eb
from 60 kBT to 80 kBT, enhancing data retention time by a factor of 108
The desire to increase magnetization caused the team to investigate alternative materials. In tests, devices formed of modified cobalt iron boron (CoFeB) alloys combined with a magnesium-oxide tunnel barrier display yielded Eb
50 to 70 kbT
for Jc ≈
The benefits of the Everspin team’s material development can be seen in the plots of write error rate (WER) as a function of voltage for various materials, including the optimized CoFeB material described above (see figure 2).
Figure 2: Plots of write error rate (WER) as a function of voltage greater cell-to-cell consistency for the optimized material (right) than for conventional materials.
The team used the optimized CoFeB material with a 90-nm CMOS process to fabricate a 64-Mb DDR3 ST-MRAM circuit. With an eight-bank architecture to minimize latency, the device demonstrated a sequential data rate of 1.6GT/s. In tests with a March6N pattern at 1.5V VDD, the 64-Mb device demonstrated zero fails (see figure 3). Although the classical MTJ features magnetization parallel to the film plane of the magnetic layers, MTJs with perpendicular magnetization may provide better Eb
at smaller dimensions required for higher density chips. This approach also simplifies manufacturing because it allows the use of circular rather than asymmetric bit shapes.
Figure 3: A 16-Mb subset of the 64-Mb ST-MRAM device tested with a March6N test pattern over 10-mV increments demonstrates failure levels of zero (green) or less than zero (red).