Design Article
Scaling directions for 2D, 3D NAND flash cells
Akira Goda and Krishna Parat, Micron Technology
1/7/2013 2:04 PM EST
Editor’s note: This work was first presented at the 2012 IEEE International Electron Devices Meeting (IEDM) and appears here courtesy of the IEEE. For more information about IEDM 2013 (Washington DC; December 9-11), click here.
Abstract
This paper describes NAND cell scaling directions for 20 nm and beyond. Many of the 2D NAND cell scaling challenges can be resolved by a planar floating gate (FG) cell. Scaling directions and key technology requirements for 3D NAND are also discussed.
2D NAND Cell Scaling
Structure
Figure 1 shows cross sections of a wrap FG cell and a planar FG cell. The increase of aspect ratio (AR) is a key limiter for the wrap FG cell scaling (see figure 2). A.R. becomes better than 10 for both the word-line and the bit-line directions in a sub-20-nm wrap cell. The planar cell eliminates this limitation [1].
E-field
Reliability degradation due to increased E-field is another scaling limitation. Floating gate and control gate (CG) widths reduce with cell scaling. This creates sharp tips on FG and CG that cause unwanted electron injection from FG to CG [2] and CG to active area (AA; see figure 3). Electron trapping due to the CG to AA injection accumulates during program/erase (P/E) cycling and limits cell cycling capability. The planar cell overcomes this issue and realizes a high cycling capability.
Vt window
NAND cell needs a wide P/E threshold voltage (Vt) window and a wide program disturb Vt window to enable multi-level-cell (MLC; see figure 4). As the cell is scaled down, a larger intrinsic Vt window is required in order to compensate for the increased single pulse program Vt distribution and cell-to-cell interference.
Cycling stress window and cell-to-cell interference
The erase Vt has to be deeper as the cell-to-cell interference increases (see figure 4). This increases oxide stress during cycling. The planar cell can reduce oxide stress due to the small cell-to-cell interference (see figure 5) and enhance cycling capability.
Abstract
This paper describes NAND cell scaling directions for 20 nm and beyond. Many of the 2D NAND cell scaling challenges can be resolved by a planar floating gate (FG) cell. Scaling directions and key technology requirements for 3D NAND are also discussed.
2D NAND Cell Scaling
Structure
Figure 1 shows cross sections of a wrap FG cell and a planar FG cell. The increase of aspect ratio (AR) is a key limiter for the wrap FG cell scaling (see figure 2). A.R. becomes better than 10 for both the word-line and the bit-line directions in a sub-20-nm wrap cell. The planar cell eliminates this limitation [1].
Fig. 1: Cross-sections of a conventional wrap FG cell (a) and
an Intel-Micron 20-nm planar FG cell (b).
an Intel-Micron 20-nm planar FG cell (b).
Figure 2: Aspect ratio increase with scaling. AR is greater than 10
for both the word-line and the bit-line directions in a
sub-20-nm wrap cell (solid: gate, open: CG fill).
for both the word-line and the bit-line directions in a
sub-20-nm wrap cell (solid: gate, open: CG fill).
E-field
Reliability degradation due to increased E-field is another scaling limitation. Floating gate and control gate (CG) widths reduce with cell scaling. This creates sharp tips on FG and CG that cause unwanted electron injection from FG to CG [2] and CG to active area (AA; see figure 3). Electron trapping due to the CG to AA injection accumulates during program/erase (P/E) cycling and limits cell cycling capability. The planar cell overcomes this issue and realizes a high cycling capability.
Figure 3: Floating gate/control gate poly width and electric field scaling.
Vt window
NAND cell needs a wide P/E threshold voltage (Vt) window and a wide program disturb Vt window to enable multi-level-cell (MLC; see figure 4). As the cell is scaled down, a larger intrinsic Vt window is required in order to compensate for the increased single pulse program Vt distribution and cell-to-cell interference.
Cycling stress window and cell-to-cell interference
The erase Vt has to be deeper as the cell-to-cell interference increases (see figure 4). This increases oxide stress during cycling. The planar cell can reduce oxide stress due to the small cell-to-cell interference (see figure 5) and enhance cycling capability.
Figure 4: Vt window definitions and requirements. P/E window
of an average cell has to be much wider than the product Vt window
to support single pulse Vt distributions and interference.
Figure 5: Cell to cell interference scaling. Approximately 30% total
interference reduction is achieved with the planar cell.
of an average cell has to be much wider than the product Vt window
to support single pulse Vt distributions and interference.
Figure 5: Cell to cell interference scaling. Approximately 30% total
interference reduction is achieved with the planar cell.
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