Program/erase Vt window and programming slope
A nitride-based cell
also has the advantages of structure scalability and interference
reduction. However, one of the known challenges for the nitride based
cell has been the poor P/E characteristics [3-4]. A poor P/E window
precludes MLC (see figure 4) and a poor programming slope degrades the
program disturb window  (see figure 6).
Figure 6: Programming slope impact on program disturb window.
P/E window and program slope are demonstrated in the case of the planar
FG cell (see figure 7). Both of these are critical for enabling a
highly reliable MLC NAND. Excellent cycling endurance characteristics
are also demonstrated (see figure 8).
Figure 7: Program and erase characteristics of a 20-nm planar FG cell.
Figure 8: Endurance characteristics of a 20-nm planar FG cell.
I compares 2D NAND cell scalability from the standpoint of Vt window,
placement width, and process integration. As can be seen from here, the
planar FG cell is the best solution for 20 nm and beyond.
2D NAND cell scaling limit
planar FG cell very effectively extends NAND cell scaling by removing
some of the physical and electrical scaling constraints. As the physical
cell size is scaled down further, cell noise (interference, random
telegraph signal (RTS), statistical fluctuation, and data retention) and
WL-WL E-field increase, and will eventually limit 2D NAND scaling .