Design Article
Addressing the challenges of transition to DDR4
Fred Rastgar and Tom Rossi, InStryde LLC
1/22/2013 1:00 PM EST
DDR4, the latest JEDEC evolution in DRAM interfaces, promises significantly lower power consumption in compliant products and systems compared to its DDR3 predecessor, as well as double the maximum performance. Along with several traditional upgrade areas such as PCB layout guidelines, operating and signaling voltage levels, DDR4 offers a broad range of control parameters that can deliver a level of performance and power savings not available to other DRAM technologies. These benefits combine to make DDR4 an ideal solution for numerous applications ranging from high performance computing and supercomputers to smaller, power-constrained mobile devices.
Bill Gervasi, memory technology analyst with Discobolus Designs, and active member of the JEDEC standards committee, has stated: "DDR4 memory technology offers many advances in terms of performance and lower power operation than the previous DDR3 technology. 2013 is shaping up as a critical period for DDR4 with its advanced silicon process technology as we see a broad range of system application designs aimed at delivering optimum performance and power savings.”
Memory market analysts anticipate DDR4 will achieve approximately 50% market penetration by the 2015/2016 timeframe. Managing, measuring, and optimizing the full range of DDR4 capabilities will require some changes to the engineering and instrumentation techniques applied across the full lifecycle of the product, however. This article examines key technical challenges designers face in transitioning to DDR4. We will also explore several useful methods to verify initial design and compliance to the specification, as well as non-intrusive techniques to monitor the DDR4 interface. These new techniques can be used to qualify different memory DIMM sources, as well as help sustaining engineering groups to verify system operations over the entire product life cycle.
DDR4 technical overview
The JEDEC DDR4 specification released in September of 2012 presents a number of enhancements over its DDR3 predecessor. As with most DRAM technology transitions, DDR4’s primary benefit comes from the transition of DRAM memory components to the latest silicon process technologies. DDR4 has adopted a 1.2-V supply, compared to a 1.5-V supply for DDR3 memory devices, significantly reducing its power consumption profile. DDR4 data transfer rates are expected to start at a minimum of 1600 MT/s, increasing beyond 3200 MT/s over time. In contrast, DDR3 does not specify speeds above 2133 MT/s (although some vendors have forged new frontiers using over-clocking techniques). For the near term, both DDR3 and DDR4 can provide suitable solutions within a common technical performance spectrum, whereas DDR4 is the clear choice for those applications that require a longer performance runway.
Memory technologies such as DDR, DDR2, DDR3, and even DDR4 were intentionally designed to be neither backward nor forward compatible with previous-generation DRAM chips. DDR4 introduces a 284-pin DIMM interface, versus the 240-pin connector used in previous generation DDR DRAMs. Furthermore, DDR4 drastically changes the memory physical interface, replacing the multi-drop bus topology with a point-to-point interface that requires each channel in the memory controller to be connected to a single module. As a result, platforms designed with newer DDR4 memory technology will require new chipsets, thus potentially increasing risk exposure for design and verification.
Initially targeted for the server market, DDR4 adopts a number of enhancements intended to deliver better performance, power, and reliability, plus accessibility, and serviceability (RAS) compared to DDR3. These enhancements present a unique opportunity for designers to achieve significant performance improvement and power reduction in the long term, while in the near term exposing significant challenges (see table 1).
The DDR4 memory interface uses a pseudo open-drain (POD) I/O structure, which is intended to deliver more relaxed timing margins with lower power consumption. The anticipated higher transfer rates mandate tighter timing margins to support normal variations in memory DIMMs, however, thus impacting the IP and memory controller designs used for DDR4.
DDR4 introduces a number of power saving enhancements such as programmable column address strobe (CAS) to address latency that can be used to improve system power efficiency. These features pose opportunities for creative power-saving techniques; at the same time, they can also add significant verification complexities for system designers, firmware developers, and software designers.
Lastly, data transfer rates for DDR4 and DDR3 should overlap for the foreseeable future, with DDR4 possessing a longer performance runway. It is quite conceivable for a DDR4 platform to deliver moderate power savings versus a comparable DDR3 design, but possibly at the expense of lower memory bandwidth performance. The system design challenge in this case is to design highly tuned, platforms that leverage the power saving and RAS enhancements of DDR4 while delivering competitive and comparable performance.
Bill Gervasi, memory technology analyst with Discobolus Designs, and active member of the JEDEC standards committee, has stated: "DDR4 memory technology offers many advances in terms of performance and lower power operation than the previous DDR3 technology. 2013 is shaping up as a critical period for DDR4 with its advanced silicon process technology as we see a broad range of system application designs aimed at delivering optimum performance and power savings.”
Memory market analysts anticipate DDR4 will achieve approximately 50% market penetration by the 2015/2016 timeframe. Managing, measuring, and optimizing the full range of DDR4 capabilities will require some changes to the engineering and instrumentation techniques applied across the full lifecycle of the product, however. This article examines key technical challenges designers face in transitioning to DDR4. We will also explore several useful methods to verify initial design and compliance to the specification, as well as non-intrusive techniques to monitor the DDR4 interface. These new techniques can be used to qualify different memory DIMM sources, as well as help sustaining engineering groups to verify system operations over the entire product life cycle.
DDR4 technical overview
The JEDEC DDR4 specification released in September of 2012 presents a number of enhancements over its DDR3 predecessor. As with most DRAM technology transitions, DDR4’s primary benefit comes from the transition of DRAM memory components to the latest silicon process technologies. DDR4 has adopted a 1.2-V supply, compared to a 1.5-V supply for DDR3 memory devices, significantly reducing its power consumption profile. DDR4 data transfer rates are expected to start at a minimum of 1600 MT/s, increasing beyond 3200 MT/s over time. In contrast, DDR3 does not specify speeds above 2133 MT/s (although some vendors have forged new frontiers using over-clocking techniques). For the near term, both DDR3 and DDR4 can provide suitable solutions within a common technical performance spectrum, whereas DDR4 is the clear choice for those applications that require a longer performance runway.
Memory technologies such as DDR, DDR2, DDR3, and even DDR4 were intentionally designed to be neither backward nor forward compatible with previous-generation DRAM chips. DDR4 introduces a 284-pin DIMM interface, versus the 240-pin connector used in previous generation DDR DRAMs. Furthermore, DDR4 drastically changes the memory physical interface, replacing the multi-drop bus topology with a point-to-point interface that requires each channel in the memory controller to be connected to a single module. As a result, platforms designed with newer DDR4 memory technology will require new chipsets, thus potentially increasing risk exposure for design and verification.
Initially targeted for the server market, DDR4 adopts a number of enhancements intended to deliver better performance, power, and reliability, plus accessibility, and serviceability (RAS) compared to DDR3. These enhancements present a unique opportunity for designers to achieve significant performance improvement and power reduction in the long term, while in the near term exposing significant challenges (see table 1).
Click image to enlarge.
Table 1: DDR4 versus DDR3 key enhancements
The DDR4 memory interface uses a pseudo open-drain (POD) I/O structure, which is intended to deliver more relaxed timing margins with lower power consumption. The anticipated higher transfer rates mandate tighter timing margins to support normal variations in memory DIMMs, however, thus impacting the IP and memory controller designs used for DDR4.
DDR4 introduces a number of power saving enhancements such as programmable column address strobe (CAS) to address latency that can be used to improve system power efficiency. These features pose opportunities for creative power-saving techniques; at the same time, they can also add significant verification complexities for system designers, firmware developers, and software designers.
Lastly, data transfer rates for DDR4 and DDR3 should overlap for the foreseeable future, with DDR4 possessing a longer performance runway. It is quite conceivable for a DDR4 platform to deliver moderate power savings versus a comparable DDR3 design, but possibly at the expense of lower memory bandwidth performance. The system design challenge in this case is to design highly tuned, platforms that leverage the power saving and RAS enhancements of DDR4 while delivering competitive and comparable performance.
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