Highly scalable vertical gate 3-D NAND

Twisted BL (split-page) 3-D VG architecture
In this work, we propose a new architecture to provide much better scalability. Figure 1(b) shows the 3D overview of the structure. In Fig. 2(a), we design VG in a twisted layout, where even/odd BL’s are arranged in opposite directions. This allows the island-gate SSL be laid out at double pitch of the BL, thus offering much larger process window. The NAND strings are therefore divided into even/odd pages accordingly, where string current flows in the opposite direction. The SEM top view of our fabricated array is shown in Figure 2(b). WL half pitch=37.5nm, BL half pitch=75nm. Each island-gate SSL controls one channel BL, while a BL pad groups a total of 16 pages (8 for even, and 8 for odd in the opposite sides). In each BL pad, there are a total of 8 (=N, where N is the stacking number) BL contacts, corresponding to the 8 (=N) different memory layers. Staircase BL contacts are fabricated for the array decoding. Note that the BL contacts are also at double pitch of the channel BL, thus allowing larger process window.

The staircase BL contacts are connected to a ML3 BL toward page buffer for sensing. Inside the array, ML1 and ML2 are used to decode the 16 (=2*N) SSL devices. The source contact is made at the line end of each channel BL, and is directly connected to a local ML1 common source line (CSL). Each memory cell is accessed by selecting the corresponding WL, ML3 BL (corresponding to the memory layer), SSL (corresponding to one channel BL). Page programming and reading are performed by simultaneously operating the many SSL’s in parallel in different units for a larger bandwidth. The page size is equal to the total ML3 BL number.



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Figure 2(c) shows the SEM bird’s eye view of our fully integrated device structure. In our process, we use the poly plug to realize the staircase BL contact and source contact. Figure 3(a) shows the BL cross sectional view. The 8-layer device is fabricated with excellent BL profile. The inset shows a zoom-in view, where each device is a double-gate TFT BE-SONOS charge-trapping device. Figure 3(b) shows the fabricated island-gate SSL for the 8-layer NAND. The island-shape layout of SSL is designed during the self-aligned double patterning process of the WL’s without additional mask. Figure 3(c) shows the WL profile. A high aspect ratio (>25) has been achieved.