Highly scalable vertical gate 3-D NAND

Advantages of 3-D VG NAND
There are several advantages of this split-page 3D VG NAND:

(1) Pitch scalability: In this work 3Xnm WL, the smallest in 3D NAND so far, is already demonstrated. Further scaling to 2D NAND limit is likely.
(2) Double-pitch of island-gate SSL, staircase BL contacts, and metal interconnect: These allow larger process window for BL pitch scalability.
(3) Low WL resistance: It is easy to fabricate silicide on top of the WL for WL RC delay reduction. In this work, we use conventional WSix.
(4) Low CSL resistance: Each source contact is directly connected to the local ML1 CSL. A low resistance CSL is critically important for NAND Flash design because the page read demands large current at CSL.
(5) Constant array efficiency at higher stacking layers: As stack number (N) increases, we can simply adjust the BL pad size (shared by 2N pages) but there is no need to expand the array area. Outside the array, only SSL decoder number increases, while WL and BL decoders are kept the same.
 
MiLC: Minimal Incremental Layer Cost for Staircase Contacts
Staircase contact is a fundamental element for all 3D memories. In a previous proposal [3], multiple trim and etch of photo resist was proposed. However, the PR trim/etch process is not accurate thus not suitable for the tight-pitch staircase contacts. Without new innovation, to make N staircase contacts may require N lithography and etching steps, which would greatly increase the cost. Overlay between lithography steps is also a concern.

We propose a novel method to greatly simplify the staircase BL contacts, as explained in Fig. 4(a). In this work we only use three masks (LA1,2,3, corresponding to 1, 2, 4 poly/oxide etch, respectively) to define a total of 8-layer stack. Sums of binary nodes of 0, 20, 21,…, 2^M-1 can generate any integer 0, 1, 2…2^M-1. To precisely define the contact position we first use an additional mask to pattern the hard mask and define the contact location precisely. The subsequent LA1, 2, 3 steps carry out the etching of 1, 2, 4 P/O respectively. A layout example is shown in Fig. 4(b). Figure 4(c) shows the fabricated staircase contacts using this novel process. Figures 4(d) and (e) shows the final BL poly plug contacts by this novel “MiLC” process. It shows excellent landing on each memory layer. SiN spacer is used to isolate poly plug and BL pad. Since MiLC allows 2^M contacts using only M masks each doubling of layer number only requires one more mask.






Electrical performances of the 8-layer 3D VG NAND array

(1) Island-gate SSL device and Cell Initial I-V: The IdVg curves of our 8-layer island-gate SSL devices are shown in Fig. 5. It shows excellent S.S. behaviors and low leakage, which is important for the NAND string operation. The typical cell initial IdVg curves are shown in Fig. 6.


Figure 5: Typical IdVg curves of the 8-layer island-gate SSL device.


Figure 6: Typical IdVg curves of the 8-layer memory cells.

(2) Programming performance and inhibit of the 8-layer device: Figure 7 shows the ISPP programming and self-boosting inhibit of the 8-layer device. Every memory layer (from PL1 to PL8) can be successfully programmed with memory window greater than 6V, leaving other layers well inhibited.


Click image to enlarge.