Design Article
Highly scalable vertical gate 3-D NAND
Shih-Hung Chen, Hang-Ting Lue, et al., Macronix International Co.
2/4/2013 4:20 PM EST
Electrical performances (cont.)
(3) Block erasing performance: The block erase method is to apply a large positive bias (~+13V) at CSL and BL’s, while keeping all WL’s=0V. The SSL’s and GSL’s are applied a moderate positive bias (~+6V) to offer suitable GIDL-induced ease with minimized disturb to SSL and GSL. The erasing performance is shown in Fig. 8.
Figure 8: Block erase operation. All memory cells can be erased by WL’s=0V, CSL=BL’s= +13V. SSL’s = GSL’s =Vpass2= ~ +6V. All memory layers and all WL’s can be erased together.
(4) Number of programming (NOP) stress: For 3D VG NAND Flash, every WL has 2N pages. Thus to complete the programming for one WL, every page must endure a total NOP = 2N-1 programming stress. The typical NOP performance of our split-page VG NAND device is shown in Fig. 9. It shows the capability to sustain a high NOP = 64 stressing.
Click image to enlarge.
(5) Vpass disturb: Vpass disturb is critically important for 3D NAND Flash. Since every WL has 2N pages and there are 64 WL’s, to complete a block operation the Vpass disturb stress is over 200msec for programming. Likewise, for a 100K read disturb criterion, the total stress time is over 10000 sec. Figure 10 shows the Vpass stress performance of our VG NAND at various biases. It shows enough window to sustain Vpass stress during programming. Figure 11 compares the Vpass stress of planar SONOS (VG) and nano-wire SONOS (VC). Although the curved channel of VC has field enhancement (FE) effect that allows faster speed at lower voltage, however, the Vpass disturb is also enhanced by the same FE effect, which limits the Vpass window. On the other hand, VG NAND has planar ONO that minimizes the Vpass disturb and is more reliable.
Figure 10: Vpass stress characteristics of 3D VG NAND device. After block erase, a 200msec or 2sec stress is applied at various bias voltages. For a typical 200msec Vpass stress criterion, 3D VG shows small Vpass disturb at Vpass<11V.
Figure 11: Simulated Vpass stress of planar SONOS (3D VG) and nano-wire SONOS (3D VC, [3]) at channel diameter=20nm. The nano-wire SONOS has field enhancement factor (FE) of around 1.7, and it shows much larger Vpass disturb than the planar SONOS. Vpass disturb is critically important in 3D NAND because one WL would have many pages, thus Vpass disturb is much higher than 2D NAND for both programming and reading and should be carefully minimized.
Summary
Successful 8-layer tight-pitch 3DVG NAND has been demonstrated. Figure 12 shows that VG NAND can provide 1Tb memory at 25nm half-pitch with only 32 stacked layers. For a vertical channel (VC) NAND nearly 100 layers are needed to reach the same memory density.
Figure 12: The available memory density for 3D VG at various technology nodes and stacked layer number within 100mm2 area. For the split-page 3D VG, we assume a constant 60% array core efficiency. A vertical channel architecture with 43nm 6F2 cell size and 90% array core efficiency is compared. We assume MLC (2b/c) for all devices.
References:
[1] H.T. Lue, T.H. Hsu, Y.H. Hsiao, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, S.Y. Wang,
J.Y. Hsieh, L.W. Yang, T. Yang, K.C. Chen, K.Y. Hsieh, and C.Y. Lu, “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device”, VLSI Symposia on Technology, session, pp. 131-132, 2010.
[2] ITRS roadmap, NAND Flash memory, 2011.
[3] R. Katsumata, M. Kito, Y. Fukuzumi, M. Kido, H. Tanaka, Y. Komori, M. Ishiduki, J. Matsunami, T. Fujiwara, Y. Nagata, L. Zhang, Y. Iwata, R. Kirisawa, H. Aochi and A. Nitayama, ” Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices”, VLSI Symposia on Technology, pp. 136-137, 2009.
[4] W. Kim, S. Choi, J. Sung, T. Lee, C. Park, H. Ko, J. Jung, I. Yoo, and Y. Park, ” Multi-Layered Vertical Gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage”, VLSI Symposia on Technology, pp. 188-189, 2009.
[5] K.P. Chang, H.T. Lue, C.P. Chen, C.F. Chen, Y.R. Chen, Y.H. Hsiao, C.C. Hsieh, S.H. Chen, Y.H. Shih, T. Yang, K.C. Chen, K.Y. Hsieh, C.H. Hung, and C.Y. Lu, “An Efficient Memory Architecture for 3D Vertical Gate (3DVG) NAND Flash Using Plural Island-Gate SSL Decoding and Study of Its Program Inhibit Characteristics”, International Memory Workshop (IMW), pp. 25-28, 2012.
[6] C.H. Hung, H.T. Lue, K.P. Chang, C.P. Chen, Y.H. Hsiao, S.H. Chen, Y.H. Shih, K.Y. Hsieh, M. Yang, J. Lee, S.Y. Wang, T. Yang, K.C. Chen, and C.Y. Lu, “A Highly Scalable Vertical Gate (VG) 3D NAND Flash with Robust Program Disturb Immunity Using a Novel PN Diode Decoding Structure”, VLSI Symposia on Technology, session 4B-1, pp.68-69, 2011.
(3) Block erasing performance: The block erase method is to apply a large positive bias (~+13V) at CSL and BL’s, while keeping all WL’s=0V. The SSL’s and GSL’s are applied a moderate positive bias (~+6V) to offer suitable GIDL-induced ease with minimized disturb to SSL and GSL. The erasing performance is shown in Fig. 8.
Figure 8: Block erase operation. All memory cells can be erased by WL’s=0V, CSL=BL’s= +13V. SSL’s = GSL’s =Vpass2= ~ +6V. All memory layers and all WL’s can be erased together.
(4) Number of programming (NOP) stress: For 3D VG NAND Flash, every WL has 2N pages. Thus to complete the programming for one WL, every page must endure a total NOP = 2N-1 programming stress. The typical NOP performance of our split-page VG NAND device is shown in Fig. 9. It shows the capability to sustain a high NOP = 64 stressing.
Click image to enlarge.
Figure 9: (a) Equivalent circuit to show the program-inhibit method. For example, to program page 0, we turn-on SSL0 by Vcc, while other SSL’s are applied a slightly negative voltage to guarantee turn-off. GSL (even) is turned-off, while GSL (odd) is turned-on. CSL is applied +Vcc to provide necessary inhibit. Page 2 (SSL2) are inhibited by floating the NAND string entirely (Mode-2). On the other hand, Page 1/3 are inhibited by precharge the channel via CSL and GSL (Mode-1). (b) NOP program inhibit performance of Mode-1, where channel is pre-charged by CSL-GSL. One NOP stress corresponds to one maximum program bias inhibit stress. (c) NOP stress performance of Mode-2. Our 3D VG NAND array has excellent program inhibit performances after NOP=64 stress.
(5) Vpass disturb: Vpass disturb is critically important for 3D NAND Flash. Since every WL has 2N pages and there are 64 WL’s, to complete a block operation the Vpass disturb stress is over 200msec for programming. Likewise, for a 100K read disturb criterion, the total stress time is over 10000 sec. Figure 10 shows the Vpass stress performance of our VG NAND at various biases. It shows enough window to sustain Vpass stress during programming. Figure 11 compares the Vpass stress of planar SONOS (VG) and nano-wire SONOS (VC). Although the curved channel of VC has field enhancement (FE) effect that allows faster speed at lower voltage, however, the Vpass disturb is also enhanced by the same FE effect, which limits the Vpass window. On the other hand, VG NAND has planar ONO that minimizes the Vpass disturb and is more reliable.
Figure 10: Vpass stress characteristics of 3D VG NAND device. After block erase, a 200msec or 2sec stress is applied at various bias voltages. For a typical 200msec Vpass stress criterion, 3D VG shows small Vpass disturb at Vpass<11V.
Figure 11: Simulated Vpass stress of planar SONOS (3D VG) and nano-wire SONOS (3D VC, [3]) at channel diameter=20nm. The nano-wire SONOS has field enhancement factor (FE) of around 1.7, and it shows much larger Vpass disturb than the planar SONOS. Vpass disturb is critically important in 3D NAND because one WL would have many pages, thus Vpass disturb is much higher than 2D NAND for both programming and reading and should be carefully minimized.
Summary
Successful 8-layer tight-pitch 3DVG NAND has been demonstrated. Figure 12 shows that VG NAND can provide 1Tb memory at 25nm half-pitch with only 32 stacked layers. For a vertical channel (VC) NAND nearly 100 layers are needed to reach the same memory density.
Figure 12: The available memory density for 3D VG at various technology nodes and stacked layer number within 100mm2 area. For the split-page 3D VG, we assume a constant 60% array core efficiency. A vertical channel architecture with 43nm 6F2 cell size and 90% array core efficiency is compared. We assume MLC (2b/c) for all devices.
References:
[1] H.T. Lue, T.H. Hsu, Y.H. Hsiao, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, S.Y. Wang,
J.Y. Hsieh, L.W. Yang, T. Yang, K.C. Chen, K.Y. Hsieh, and C.Y. Lu, “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device”, VLSI Symposia on Technology, session, pp. 131-132, 2010.
[2] ITRS roadmap, NAND Flash memory, 2011.
[3] R. Katsumata, M. Kito, Y. Fukuzumi, M. Kido, H. Tanaka, Y. Komori, M. Ishiduki, J. Matsunami, T. Fujiwara, Y. Nagata, L. Zhang, Y. Iwata, R. Kirisawa, H. Aochi and A. Nitayama, ” Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices”, VLSI Symposia on Technology, pp. 136-137, 2009.
[4] W. Kim, S. Choi, J. Sung, T. Lee, C. Park, H. Ko, J. Jung, I. Yoo, and Y. Park, ” Multi-Layered Vertical Gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage”, VLSI Symposia on Technology, pp. 188-189, 2009.
[5] K.P. Chang, H.T. Lue, C.P. Chen, C.F. Chen, Y.R. Chen, Y.H. Hsiao, C.C. Hsieh, S.H. Chen, Y.H. Shih, T. Yang, K.C. Chen, K.Y. Hsieh, C.H. Hung, and C.Y. Lu, “An Efficient Memory Architecture for 3D Vertical Gate (3DVG) NAND Flash Using Plural Island-Gate SSL Decoding and Study of Its Program Inhibit Characteristics”, International Memory Workshop (IMW), pp. 25-28, 2012.
[6] C.H. Hung, H.T. Lue, K.P. Chang, C.P. Chen, Y.H. Hsiao, S.H. Chen, Y.H. Shih, K.Y. Hsieh, M. Yang, J. Lee, S.Y. Wang, T. Yang, K.C. Chen, and C.Y. Lu, “A Highly Scalable Vertical Gate (VG) 3D NAND Flash with Robust Program Disturb Immunity Using a Novel PN Diode Decoding Structure”, VLSI Symposia on Technology, session 4B-1, pp.68-69, 2011.
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greenpattern
2/5/2013 11:58 PM EST
These 3D-NAND structures essentially use fork-shaped capacitors - that needs to be taken into account.
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resistion
2/6/2013 9:16 AM EST
Fork shape?
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greenpattern
2/6/2013 11:38 AM EST
The WL's and BL's are not individual lines but linked within the same plane, forming forks. The BL fork actually touches source line, not actual fork shape sorry. Voltage over entire plane being same, the capacitive coupling to neighboring plane is serious risk.
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resistion
2/10/2013 11:33 AM EST
So there is larger capacitance between BL's or WL's than in the gate stack itself?
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