Memory 101: What you need to know about FRAM, part 2

Bit Line Capacitance Ratio
The voltage generated on the bit line by the two memory states of the ferroelectric capacitor is determined by the capacitance of the bit line relative to the area of the ferroelectric capacitor. This relationship is the bit-line-to-capacitance (BLC) ratio. Equivalent capacitances for the two memory states of the ferroelectric capacitor may be calculated by dividing the expected charge per state by the read voltage. Assuming 10 µC/cm² and 50 µC/cm² for the two states at 2 V for a 0.4 µm² capacitor, the equivalent capacitances are 20 fF and 100 fF. The sense voltages and their differential are then set by adjusting the length of the bit line. Once the bit line length is set, the addition of the sense amps, line drivers, and address decode sets the size of the die.

The BLC ratio has an impact on reliability because it determines the smallest memory signal the sense amplifiers can detect after reliability losses. A lower ratio allows a smaller differential to be detected but makes the die larger for the same number of bits. On the 512-bit ECD at Krysalis, since we knew little about the signal that would occur after integration, we set the BLC very low at 0.5 to 1. This meant that the sense voltages were literally in the volts and the initial differential voltage was about a volt. In today’s FRAMs with little to no fatigue or imprint, the memory polarizations will not change much or at all over the lifetime of the product, so very high BLC ratios can be used. This results in sense voltages similar to those of DRAMs.

Fatigue
Not all ferroelectric capacitors fatigue. Those that do fatigue will permanently lose a little of their DOWN polarization (see figure 6) on every cycle around the hysteresis loop. The amplitude of the UP state is unaffected by cycling. Fatigue arises from the combination of the ferroelectric composition with its electrode material. The 512ECD used PZT with platinum electrodes and it did suffer fatigue. Today’s PZT-based FRAMs use conductive   oxides for electrodes to extend their cycling lifetimes out beyond our ability to test. SBNT does not fatigue significantly with platinum electrodes. If cycling fatigue does occur in its capacitors, the lifetime of an FRAM can be extended by careful design choices. Despite the strong fatigue characteristics of its capacitors, the 512ECD could reach almost 10¹² cycles because of the 0.5:1 BLC ratio.


Imprint and Retention
Loss of stored data is every memory designer’s nightmare. It turns out that a properly designed FRAM will never lose data due to the ferroelectric capacitor losing retention. Instead, after years, we realized that the problem was just the opposite: the longer a state is stored in a ferroelectric capacitor, the less likely the capacitor will accept the opposite state. The original data becomes imprinted. This problem was first recognized and publicized by Dr. Norm Abt of National Semiconductor in 1992.[4]

For FRAM, imprint turned out to present a far more serious issue than fatigue. Imprint starts the instant each capacitor sees its first voltage, which occurs in production test, and its rate increases with temperature. Fortunately, there are ferroelectric composition and electrode combinations that do not imprint or fatigue. These are the structures used in commercial FRAM modules today.

Process Integration
Integrating ferroelectric capacitors onto CMOS or bipolar devices is the most expensive part of building an FRAM device. All commercial FRAMs use ceramic ferroelectric capacitors. MOS transistors, filled vias, and bipolar Schottky diodes do not tolerate well the temperatures necessary to densify ferroelectric ceramics. Attempts have been made to use organic ferroelectric capacitors that form at much lower temperatures, but those efforts have so far not been successful in production. A balance between the thermal needs of ceramic ferroelectric materials and the thermal limits of CMOS devices can be reached. The same might be true for bipolar processes but there is no effort presently underway to build FRAM on bipolar platforms. That situation may change in the future to create space-qualified radiation-hard non-volatile memories. Ferroelectric capacitors simply are not affected by the level of radiation that would erase floating gate memories or latch up CMOS.

Ferroelectric capacitors suffer from exposure to CMOS processes. Hydrogen ions interfere with the switching of ferroelectric capacitors. Hydrogen ions are single protons that diffuse through almost anything and their charge attracts them to ferroelectric domains. The hydrogen can be baked out, but CMOS fabrication processes use hydrogen environments constantly. Only aluminum oxide and some variants appear to be dense enough to slow down the diffusion of hydrogen into the ferroelectric capacitor proper. All FRAM capacitors, no matter the material type, are encapsulated with some type of dense passivation after baking out the hydrogen to prevent further accumulation of hydrogen protons during the forming gas anneal and plastic packaging.

The 512ECD was fabricated with a relatively simple memory cell layout similar to those used for the first FRAM products in the 1990s by Ramtron and Fujitsu. After the MOS transistors were fabricated and the wafer covered with glass, the ferroelectric capacitor was built on a flat spot next to its pass transistor. The two were connected together with metal lines. This approach has high yield but a very large cell. Commercially viable FRAM requires the positioning of the capacitor above the transistor, connecting to the transistor source contact through a filled via. Filled vias are very sensitive to thermal budget above 400°C. Minimizing that thermal budget while achieving high quality hysteresis loops with no interfacial reactions between the capacitor and the via fill material is a daunting challenge, one that has been solved.