Toshiba tweak reduces SRAM standby power by 85%

LONDON – Leading memory chip company Toshiba Corp. has announced the development of a technique to reduce the power consumption of embedded SRAM by up to 85 percent in standby mode. The technology is expected to be useful for use in smartphones and other battery-operated equipment, Toshiba said.

One advantage of SRAM over some other memory types is that it can be integrated with logic and, unlike DRAM, it can retain data with the clock removed and without refresh. However, the SRAM does still require that the power supply is present and SRAM is not particularly tolerant of voltage reduction. Hence, many applications use off-chip non-volatile memory.

Toshiba has now announced a design technique that significantly reduces active and standby power consumption in temperatures ranging from room temperature to high temperature. This is done by using a bit-line power calculation circuit and a digitally-controlled retention circuit.  

A prototype has been shown to reduce active and standby power consumption at 25 degrees C by 27 and 85 percent respectively. It is not clear from the company's statement how much die area the added circuits take up but Toshiba presented the development in a paper at the 2013 International Solid-State Circuit Conference in San Francisco, CA on Feb. 20.

The bit-line power calculator predicts the power consumption of bit lines by using replicated bit lines to monitor the frequency of the ring oscillator. It minimizes the current consumption of the SRAM in certain conditions, Toshiba said. The digitally-controlled retention circuit decreases standby power by periodically updating the size of a buffer memory.

While the technique is of questionable value when a processor is operating at peak performance and therefore high temperature a great deal of mobile equipment spends a lot of time at low performance. At clock frequencies of tens of megahertz and SRAM temperature, whether on-chip or off-chip, remaining around room temperature the active and leakage power are comparable, Toshiba said. It is therefore beneficial for the battery life of equipment to save power under these conditions.

Toshiba did not indicate how soon the technique might be deployed in commercial logic or memory components.


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