Integrating memory with controller
Adding memory to the TN4010 was not as simple as integrating the OTP NVM into the controller chip since customers have expectations of being able to revise the contents without restriction. A bit-for-bit replacement would not have met this expectation. What made the tradeoff possible? The answer lies in the contents of the external EEPROM/flash memory and how it is written and accessed.
The external serial EEPROM/flash is used to store a set of unique identifiers and configuration information like the media access control (MAC) address, the unique identifier assigned to the network interfaces for communications on the physical network segment. Assigned to the NIC or LOM manufacturer by the IEEE, a MAC address encodes the manufacturer's registered identification number and is called the burned-in address. The MAC address can be written by the SoC manufacturer—in this case, Tehuti Networks—or by the NIC and LOM OEM.
As a default, Tehuti Networks writes a MAC address into the controller’s 8092-bit on-chip antifuse OTP NVM. To ensure that Tehuti customers may optionally write their own unique IDs, the on-chip memory includes sufficient room to store additional configurations. The memory is divided into eight separate segments of 1024 bits each. The first is optionally written by Tehuti and the remaining seven are available to their NIC and LOM customers.
As with any PCI Express device, the TN4010 components contain unique vendor and sub-vendor identifiers (VIDs and SVIDs), and device and sub-device identifiers (DIDs and SDIDs) that are written once and never changed. Thus, in addition to the MAC address, the NIC and LOM OEM may customize these identifiers to allow loading of unique software drivers.
Altogether, this device configuration data consumes no more than 256 bits in any one segment. The customer may use the additional space in a segment to store any preset register values, software configuration flags, or other system information in the design. This data is used to initialize the network subsystem to a known state. Furthermore, at any stage before shipment, the OEM can customize this configuration data up to seven times.
In addition, the TN4010 offers a lock mechanism that allows the OEM to close the NVM to any subsequent write operation, thus enabling secure applications that cannot allow modification to the pre-defined configuration.
Tehuti provides a copy-ready reference design that OEMs can use to evaluate the controller and software tools that allow the OEM to program the on-chip NVM. The Tehuti controller chip also contains the I/O pins that would allow the customer to use an optional external serial EEPROM/flash memory if they choose.
With the addition of on-chip antifuse OTP NVM, the TN4010 10GbE controller provides NIC and LOM system manufacturers with a means to reduce system cost, power demand, and package size compared to alternative offerings. This makes the TN4010 well suited for accelerating mass-market migration from 1GbE to 10GbE.
About the author
As COO for Tehuti Networks Ltd., Nir Sever brings with him more than 23 years of technological and managerial experience in advanced VLSI engineering. Prior to joining Tehuti, Nir served for nine years as the Senior Director of VLSI Design and Technologies for Zoran Corp., where he was responsible for driving Zoran silicon technologies and delivering more than 10 new silicon products each year. Prior to Zoran, Nir held various managerial and technological VLSI roles at 3dfx Interactive, GigaPixel Corp., Cadence Design Systems, ASP Solutions, and Zoran Microelectronics. Nir is a BSEE graduate from the Technion—Israel Institute of Technology.