When JEDEC Solid State Technology Association announced the initial publication of its widely anticipated DDR4 SDRAM standard, JESD79-4, the voluminous document described the DDR4 SDRAM device in exacting detail. However, JESD79-4 was not intended as a tutorial on system design or to provide explanations as to if and how specific system designs should be migrated to utilize DDR4 SDRAM devices, so it’s left to the readers to imagine the possible advantages of the technology at the system level. Consequently, a knowledge gap exists between the presentation of the technical details in JESD79-4 and understanding the underlying motivations and rationale that led to the standard. In an attempt to bridge that knowledge gap, let’s explain some of the purpose of the DDR4 SDRAM device, and frame it in the context of system level trends. By understanding the underlying motivations of the DDR4 SDRAM device specification, engineers and program managers can better decide whether or not their current and future designs should migrate to support DDR4 SDRAM devices.
The DDR4 SDRAM device is an evolutionary device that improves upon the DDR3 SDRAM generation in terms of capacity, performance scalability, power efficiency, as well as system-level reliability, availability and serviceability (RAS). At the same time, DDR4 must minimize changes that hinder design migration and adoption of the new industry-standard component.
Let’s explore the distinctions between DDR3 and DDR4, how the latter enhances system-level capacity and performance scalability, and DDR4’s various innovations that improve power efficiency. Then we’ll look at the various techniques designed into a DDR4 SDRAM device that improve system-level RAS. Finally, we’ll address the challenges of migrating DDR3 memory systems to DDR4 SDRAM.Improved capacity and performance scalability
One subtle and yet important difference that distinguishes the two is that DDR4 is organized differently from DDR3—specifically in the area of how DDR4 is designed to support high-speed multi-core processors. The 8-Gb DDR4 SDRAM device with 4-bit-wide data bus interface (x4), for example, is internally organized as a device with four bank groups and four banks in each bank group. Within each bank in the 8-Gb x4 DDR4 SDRAM device, there are 131,072 (217
) rows, with 512 bytes of DRAM cells per row. Compared to the 8-Gb x4 DDR3 SDRAM device, which has eight independent banks, 65536 (216
) rows per bank, and 2048 bytes per row, the 8-Gb x4 DDR4 SDRAM device has more banks. Moreover, the 8-Gb x4 DDR4 SDRAM device has significantly smaller row sizes than the 8-Gb x4 DDR3 SDRAM device, meaning that the 8-Gb x4 DDR4 SDRAM device can cycle through different banks at a far higher rate than could the 8-Gb x4 DDR3 SDRAM device.
A comparison of a DDR3 LRDIMM to a DDR4 RDIMM shows that the largest DDR3 SDRAM module may be constructed with quad die packages (QDP) of 8Gb x4 DRAM devices, reaching a theoretical maximum capacity of 128GB for a single-memory module (see figure 1). Figure 1 also shows that a DDR4 RDIMM may be constructed with upwards of eight-high DRAM stacks, supporting a theoretical maximum capacity of 512 GB per module. Furthermore, this diagram illustrates that the pin count on the DDR4 memory module has been increased to 284 pins, to support the higher addressing capability, as well as a 1:1 signal-to-ground ratio for the data bus (DQ) interface signals. Overall, figure highlights a few of the component and module-level changes that enable the DDR4 memory module to simultaneously support higher capacity and higher performance than the DDR3 memory module.
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Figure 1: Comparison of a DDR4 SDRAM module (bottom) to a DDR3 SDRAM module (top) shows the increased pin count for DDR4 memory modules, the decreased pitch, and the 1:1 signal-to-ground ratio for the data bus interface signals. Improved power efficiency
Another major area that the DDR4 SDRAM specification targeted for improvement over the DDR3 SDRAM specification is in the area of power efficiency. Aside from further reducing the DRAM I/O voltage (VDDQ) from 1.35 V used by DDR3L DRAM devices to 1.2 V, the DDR4 SDRAM device also specifies that a separate VPP voltage supply be provided to support high DRAM core word line voltage requirements. The data I/O electrical interface signaling has been changed from series-stub terminated logic (SSTL) to pseudo-open drain (POD). A comparison of DDR3-style SSTL signaling to DDR4-style POD signaling highlights how the output driver drives electrical high, and the SSTL circuit incurs the cost of the I2 drive current, as well as the I1 termination current due to the center tapped termination (CTT).
Figure 2: The DDR3 output driver drives the electrical high and the SSTL circuit incurs the cost of the I2 drive current, as well as the I1 termination current due to the center tapped termination (CTT), while POD signaling of DDR4 incurs no current flow in the case of driving electrical high, allowing reducing the DDR4 power requirements.
In contrast, the DDR4-style POD signaling incurs no current flow in the case of driving electrical high. Collectively, the reduced VDDQ voltage, the use of VPP supply for boosted word line voltage, the change to POD signaling and VDDQ termination, and the previously discussed smaller row sizes that reduce activation currents lead to significant reductions in power consumption for DDR4 when compared to DDR3 SDRAM. Preliminary analysis suggests that at comparable operating data rates, a DDR4 SDRAM device has a 30% advantage in power efficiency compared to a DDR3 SDARM device. That improvement can be used to operate the DDR4 SDRAM device at higher speeds, thus attaining higher performance or reduced power consumption at comparable performance levels.