Improved reliability, availability and serviceability (RAS)
Another area that the DDR4 SDRAM device specification targeted for improvement is in the area of RAS. One example in which the DDR4 SDRAM specification improves RAS is that DDR4 device supports command and address parity error detection, as well as recovery from parity error. A second example is that the DDR4 device supports a connectivity test mode, so that a system controller can test and detect connectivity faults without needing to go through DRAM initialization sequencing. Additionally, the DDR4 register also provides enhanced RAS over the DDR3 register in that the DDR4 register can be configured to support command blocking upon detection of a parity error; that is, in the case of a command and address parity error, the DDR3 register passes the erroneous command to the DRAM devices, making error recovery difficult. In contrast, the DDR4 register blocks the erroneous command and the DDR4 SDRAM device never sees the erroneous commands in the case of address parity error, thereby reducing the complexity of the error recovery process. Additionally, the DDR4 SDRAM device specification includes some optional features such as cyclic redundancy check (CRC) protection for write data to further enhance RAS. The extensive feature set ensures that as the DDR4 SDRAM device scales further in frequency where error rates may be non-negligible, future memory systems can take advantage of the enhanced RAS features in the DDR4 SDRAM device to improve the robustness of the memory system. This enables not just error detection but also capabilities to report and recover from multiple types of errors.
The JESD79-4 specification for DDR4 SDRAM devices ushered in numerous evolutionary improvements over DDR3 SDRAM devices. The DDR4 SDRAM device and the DDR4 memory module still rely on the same single-ended signaling and system infrastructure requirements, as do DDR3 SDRAM memory systems. Various changes have been made to device organization to better facilitate migration to multi-core systems and multi-threaded applications. In essence, the various JEDEC member companies utilized the in-field learning experiences of DDR3 SDRAM memory systems, enhanced performance and capacity scaling, and significantly improved system-level RAS, while attaining improved power efficiency.
With smaller rows and better power efficiency leading to performance and power advantages, DDR4 memory devices should see broad adoption in multi-core server and workstation systems starting in 2014. Thereafter, as 8-Gb DRAM begins to see widespread adoption, DDR4 SDRAM devices should then become the dominant commodity memory type and enjoy a cost-per-bit advantage, in addition to the aforementioned performance and power advantages. Designers looking to maximize performance, power, RAS and cost-sensitive systems in next-generation servers should evaluate using DDR4 SDRAM devices as the memory type of choice.
1. In response to widespread demand for comprehension and clarity on the topic of the DDR4 SDRAM specification, JEDEC has hosted two-day DDR4 Technical Workshops that explored, explained and clarified the various design choices and motivations that resulted in the JESD79-4 DDR4 SDRAM specification. The material presented herein is sourced from one of the eight sessions presented at the Technical Workshop.
2. The DDR4 SDRAM device is organized in bank groups to facilitate continued interface data rate scaling without requiring longer burst lengths or significantly faster DRAM core cycling rates. The bank group structure requires new memory controllers that are bank-group-aware to attain full performance advantage.
3. The 8-Gb x4 DDR4 SDRAM device rated as 1600 MT/s capable has tFAW (Four-bank Activation Window) value of 20ns, a value that is half of the 8Gb x4 DDR3 SDRAM device’s tFAW value of 40ns, meaning that a 8Gb x4 DDR4 SDRAM device can open random rows in different banks at twice the rate of the comparable 8Gb x4 DDR3 SDRAM device.
4. To attain the highest capacity and data rate, the DDR3 memory system requires the use of a DDR3 LRDIMM.
5. Each DRAM package may constitute one, two, four or eight DRAM dies. Eight-high (8H) stacks would likely require through-silicon-via (TSV) technology for practical implementation. The eight-high DRAM stack definition is included as part of the 3D-stacking (3DS) specification addendum to JESD79-4.
6. The DRAM word line requires higher voltages to activate the access transistor, ensuring fast access during the on-state and ultra-low leakage during the off-state. The availability of the 2.5V VPP means that the word line voltage does not have to be inefficiently supplied (pumped up) from the 1.2V VDDQ supply, thereby improving energy/power efficiency.
7. Since there is no current flow from VDD to VDD, I3 is equal to zero. Driving low on POD circuit will draw current flow from VDD to GND.
8. The 30% figure is approximate, depending on access pattern and specific process nodes and circuit designs.
About the author
David Wang is a senior principal architect at Inphi Corp, a leading provider of high-speed semiconductor solutions for the communications and computing markets. He can be reached at firstname.lastname@example.org
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