Design Article
MIEC-based access devices go fast, small and 3-D
K. Virwani, G. W. Burr, et al., IBM
3/18/2013 10:31 AM EDT
Speed of MIEC ADs for NVM write and read (cont.)
At the much lower (5–10 µA) current levels associated with NVM reads, the pulsed response of small-array integrated MIEC ADs (see figure 7) can become difficult to unambiguously distinguish from background noise. While signal strength can be greatly increased by measuring multiple MIEC ADs in parallel, the increased parasitics and presence of unequal current division (even for slight device-to-device variations) also introduce significant uncertainty.
However, we can accurately measure such currents with the sense amplifier (SA) integrated with our large (512 kb) arrays. Although the SA has its own temporal response, we can isolate this with nearby ROM arrays integrated with polysilicon resistors, and then compare the slower response of integrated MIEC ADs through the same type of SA (see figure 8). Figure 9 combines data from the high-current measurements (see figure 4a) with these indirect measurements using the large-array SA to illustrate the highly nonlinear turn-on of MIEC devices. Although full saturation of MIEC ADs at the typical read current levels expected for future NVM reads (approximately 5 µA) is not rapid, either the application of shaped pulses (see figure 10) or a transient “overvoltage” read (green dashed circle in see figure 8) can readily allow approximately 5 µA NVM reads in much less than 1 µs using MIEC ADs.
Thickness and CD scaling of MIEC ADs
By varying the thickness of SiN into which Cu-containing MIEC material was deposited [2], thickness scaling experiments were performed on short-loop devices tested with Conductive-AFM (C-AFM, see figure 11). Over-etch into the BEC during via formation and dishing during Chemical-Mechanical Planarization (CMP) causes the minimum device thickness dmin (at the edge of the MIEC AD) to differ from (yet track with) the SiN thickness. As devices become thinner (see figure 12), the distribution of voltage margins remains mostly unchanged (see figure 13) until dmin is approximately 11 nm. Figure 14 shows a topographic AFM image and yield map of devices with an average dmin of approximately 12 nm. Figure 15 shows IV characteristics for the four neighboring devices marked in figure 14. Since the markedly leaky device with lower Vm (at 10 nA) corresponds to dmin of approximately 6.0 nm (see figure 16), both yield and voltage margin appear insensitive to thickness down to dmin approximately 11 nm.
At the much lower (5–10 µA) current levels associated with NVM reads, the pulsed response of small-array integrated MIEC ADs (see figure 7) can become difficult to unambiguously distinguish from background noise. While signal strength can be greatly increased by measuring multiple MIEC ADs in parallel, the increased parasitics and presence of unequal current division (even for slight device-to-device variations) also introduce significant uncertainty.
Figure 7 MIEC ADs integrated with 180 nm FETs and finished with M2 wiring can be tested in large arrays through an integrated 1-bit sense amplifier (SA).
However, we can accurately measure such currents with the sense amplifier (SA) integrated with our large (512 kb) arrays. Although the SA has its own temporal response, we can isolate this with nearby ROM arrays integrated with polysilicon resistors, and then compare the slower response of integrated MIEC ADs through the same type of SA (see figure 8). Figure 9 combines data from the high-current measurements (see figure 4a) with these indirect measurements using the large-array SA to illustrate the highly nonlinear turn-on of MIEC devices. Although full saturation of MIEC ADs at the typical read current levels expected for future NVM reads (approximately 5 µA) is not rapid, either the application of shaped pulses (see figure 10) or a transient “overvoltage” read (green dashed circle in see figure 8) can readily allow approximately 5 µA NVM reads in much less than 1 µs using MIEC ADs.
Figure 8: To reliably measure the temporal response of MIEC ADs at low current, the selected wordline is enabled shortly before the SA state is latched, but after the SA has otherwise stabilized on the selected bitline. Nearby ROM arrays integrated with polysilicon resistors illustrate that a brief initial portion of this response is due to the internal dynamics of the SA, with the remainder due to the MIEC AD.
Figure 9: Inferred temporal response of MIEC ADs, combining data from direct and precise high-current measurements (see figure4a) and indirect measurements using the large-array SA.
Figure 10: Application of a shaped voltage pulse directly to an integrated (small-array) MIEC AD shows that approximately 5 µA currents suitable for NVM can be obtained in less than 1 µs. Further use of “overvoltage” during MIEC AD turn-ON can be used to enable NVM read speeds much less than 1 µs, as demonstrated in the green dashed circle in figure 8.
Thickness and CD scaling of MIEC ADs
By varying the thickness of SiN into which Cu-containing MIEC material was deposited [2], thickness scaling experiments were performed on short-loop devices tested with Conductive-AFM (C-AFM, see figure 11). Over-etch into the BEC during via formation and dishing during Chemical-Mechanical Planarization (CMP) causes the minimum device thickness dmin (at the edge of the MIEC AD) to differ from (yet track with) the SiN thickness. As devices become thinner (see figure 12), the distribution of voltage margins remains mostly unchanged (see figure 13) until dmin is approximately 11 nm. Figure 14 shows a topographic AFM image and yield map of devices with an average dmin of approximately 12 nm. Figure 15 shows IV characteristics for the four neighboring devices marked in figure 14. Since the markedly leaky device with lower Vm (at 10 nA) corresponds to dmin of approximately 6.0 nm (see figure 16), both yield and voltage margin appear insensitive to thickness down to dmin approximately 11 nm.
Figure 11: Short-loop MIEC devices were fabricated with thinner SiN and/or smaller via diameters, and then tested with C-AFM.
Figure 12: Transmission Electron Micrographs (TEMs) of four representative devices with scaled SiN thicknesses. Due to over-etch into the BEC during via formation combined with dishing during CMP, the minimum device thickness dmin is located at the edge of the MIEC AD.
Figure 13: Cumulative distribution functions (CDFs) of measured Vm at 10 nA of greater than 1000 MIEC ADs corresponding to the representative devices shown in figure 12. As devices become thinner, voltage margins remain mostly unchanged until dmin is approximately 11 nm (d).
Figure 14: Topographic AFM image and yield map for MIEC AD devices with an average dmin approximately 12 nm (figures 12, 13(c)). Four neighboring devices (indicated in magenta) were cross-sectioned for TEM.
Figure 15: IV characteristics for the four neighboring MIEC ADs marked in Figure 14, showing three healthy MIEC ADs and one more leaky device with lower Vm.
Figure 16: TEMs of the marked MIEC ADs (figure 14) show that the markedly leaky device (figure 15c) corresponds to dmin of approximately 6.0 nm. Devices with dmin of approximately 11.1–12.5 nm exhibit similar low leakage and voltage margin characteristics as much thicker devices (figures 12,13).
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