Design Article
Achieving high currents on PCBs with fine-pitch SMD components
Peter Mauer,Semikron Elektronik
3/25/2011 9:19 AM EDT
In switched-mode power supply systems or other circuits used in power electronics, the demand for control circuitry to use finepitch SMD components is ever increasing. At the same time, however, high currents of more than 100A will be present across the printed circuit board. Product developers face the challenge of finding a suitable yet financially viable solution.
In power electronic systems, the PCBs used often involve challenging technical requirements that force product developers to come up with particularly creative solutions to meet these requirements. Engineering compromises in key areas have to be made, since the sensitive control circuits normally have to use standard inexpensive SMD components. This calls for fine-pitch structures for the wiring and land pattern for the components, microcontroller and FPGAs.
Fine-pitch SMD structures are now easily achieved by the majority of PCB manufacturers for copper thicknesses in the signal layers up to 35µm – see figure 1. By way of contrast, to achieve the high currents needed for a MiniSKiiP module, i.e. to achieve 120 Amps in 35µm technology, either extremely wide wiring or copper surfaces would be needed to keep heat build-up at bay.

Fig. 1: Normal 35µm stackup design.
For such thicknesses, it would be virtually impossible for product designers to comply with clearance specifications if the PCB is to be small in size and, for cost reasons, the number of layers is to be kept to a minimum. The use of standard 35µm technology can therefore be ruled out here; instead, new solutions are required. Possible compromises might be to use thick copper or wirelaid technology.
Thick cooper stackup design
To achieve a satisfactory width for the individual high-current tracks, the stackup design has to be altered while the cross-sectional area of the conductor remains unaltered. If, instead of 35µm-thick copper, the layer thickness for the outer and inner layers is increased to 70µm and 105µm, respectively, suitable conductor widths can be achieved – see figure 2.

Fig. 2: PCB layout with 70 and 105µm thick copper.
Unfortunately, it is not possible to achieve fine pitches (clearances) on the 70µm-thick outer layers at a reasonable cost. Here, the ratio of circuit board conductor width to height would result in behaviour in production that is difficult to predict. An additional 35µm layer pair would resolve this problem technically; unfortunately, however, this would negatively impact the production costs.
Alternatively, in place of SMD components, traditional components with no fine-pitch clearances could be used and 70µm-thick copper used for the outer layers. This would normally result in a larger PCB. Another problem here is that some components are only available in fine-pitch technology, meaning that circuit redesign would be necessary.
In power electronic systems, the PCBs used often involve challenging technical requirements that force product developers to come up with particularly creative solutions to meet these requirements. Engineering compromises in key areas have to be made, since the sensitive control circuits normally have to use standard inexpensive SMD components. This calls for fine-pitch structures for the wiring and land pattern for the components, microcontroller and FPGAs.
Fine-pitch SMD structures are now easily achieved by the majority of PCB manufacturers for copper thicknesses in the signal layers up to 35µm – see figure 1. By way of contrast, to achieve the high currents needed for a MiniSKiiP module, i.e. to achieve 120 Amps in 35µm technology, either extremely wide wiring or copper surfaces would be needed to keep heat build-up at bay.

Fig. 1: Normal 35µm stackup design.
For such thicknesses, it would be virtually impossible for product designers to comply with clearance specifications if the PCB is to be small in size and, for cost reasons, the number of layers is to be kept to a minimum. The use of standard 35µm technology can therefore be ruled out here; instead, new solutions are required. Possible compromises might be to use thick copper or wirelaid technology.
Thick cooper stackup design
To achieve a satisfactory width for the individual high-current tracks, the stackup design has to be altered while the cross-sectional area of the conductor remains unaltered. If, instead of 35µm-thick copper, the layer thickness for the outer and inner layers is increased to 70µm and 105µm, respectively, suitable conductor widths can be achieved – see figure 2.

Fig. 2: PCB layout with 70 and 105µm thick copper.
Unfortunately, it is not possible to achieve fine pitches (clearances) on the 70µm-thick outer layers at a reasonable cost. Here, the ratio of circuit board conductor width to height would result in behaviour in production that is difficult to predict. An additional 35µm layer pair would resolve this problem technically; unfortunately, however, this would negatively impact the production costs.
Alternatively, in place of SMD components, traditional components with no fine-pitch clearances could be used and 70µm-thick copper used for the outer layers. This would normally result in a larger PCB. Another problem here is that some components are only available in fine-pitch technology, meaning that circuit redesign would be necessary.
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vrheaume
3/25/2011 10:02 PM EDT
typo: "Thick cooper stackup design" should be "Thick copper stackup design" (cooper becomes copper)
Interesting article; I have been involved with projects that required routing some tens of amps on a PCB, and I know it's not easy...
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Sanjib.Acharya
3/27/2011 12:00 PM EDT
It is very difficult to comprehend from Figure 4. as the texts are not clearly visible.
Although it is very useful to learn about the wirelaid technology, it would be great if information about the cost premium with respect to the standard PCBs of comparable size & number of layers is provided?
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Robotics Developer
3/28/2011 2:06 PM EDT
The article hints at a solution but I am not sure the "wirelaid" approach is cost effective or achievable for most PCB fabs. I would have liked more details like cost/benefits, applicability to general (or does wirelaid need specialized) PCB fabricators, other options explored (fine pitch on a daughter card, differing copper thicknesses - thick inner layers with a thin outer). There has got to be multiple solutions to this problem but they were not presented nor explored.
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docdivakar
4/11/2011 1:32 PM EDT
I don't know what is new about "Wirelaid technology" that is being discussed here -I have seen copper plugs of all dimensions incorporated in PCB stackups for ages now!
As others commented above, the article leaves out many details. For one, I would have liked to see what reliability tests were done to address the "high" current traces. Also there is no metric describing the highest current density (A/cm^2 or similar metric) in the design that raised issues about current crowding if any.
The article overall falls short on the technical details.
Dr. MP Divakar
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hm
4/11/2011 3:39 PM EDT
Peter - Does this "Wirelaid Technology" has been approved by IPC? Most of the design and manufacturing vendor do have to comply with IPC standard. Without IPC standard, how effective will be this technology?
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HereBeDragons
4/17/2011 10:54 PM EDT
This sounds very much like a hybrid of conventional PCB wiring and the old "multiwire" system, used back in the 70-80's where components were interconnected using machine-routed insulated wires embedded in a non-conducting matrix.
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