Addressing energy consumption in the Archimedes MCU
At the extremes of energy-efficient system design, it is vital to understand the inner workings of the microcontroller itself. Incorrect use of the microcontroller and its features can easily increase energy consumption by an order of magnitude. The last section showed that active mode power and sleep mode power are the two key components requiring attention in a typical system. In this section, we explore how these sources of energy consumption are being attacked today in microcontrollers and how they will be addressed in next-generation microcontrollers.
As an example, we use a cutting edge Cortex-M3 microcontroller that has demonstrated unprecedented energy efficiency for any core, including the most efficient 8-, 16-, and 32-bit architectures. A block diagram for this research prototype microcontroller, called the Archimedes Microcontroller, is shown in figure 3 
. It includes a Cortex-M3 core along with 3 kB of retentive SRAM, 2kB of non-retentive (i.e., power-gated) SRAM, a capacitance-to- digital converter, and a temperature sensor.
Fig 3: Archimedes microcontroller block diagram
Archimedes uses several well-known techniques to reduce active mode energy. The use of the Cortex-M3 architecture, in particular, helps to address active mode energy. The Cortex-M3 is ideally suited to low active mode energy as it is a lightweight core with very few gates. Furthermore, the Cortex-M3 uses Thumb-2 technology to deliver better code density than 8-bit and 16-bit processors and can complete many typical operations in fewer clock cycles (and with less energy) than 8-bit and 16-bit processors.
Archimedes also uses several new techniques to reduce active mode energy. Most notably, Archimedes operates digital circuits at a supply voltage as low as 0.4V using an internal voltage regulator. This aggressive voltage scaling reduces the amount of charge used to represent a “1” and reduces active energy quadratically (assuming ideal voltage down-conversion).
Figure 4 confirms the dramatic active mode energy savings achieved as a result of voltage scaling (neglecting the power overhead of voltage conversion). Such aggressive voltage scaling has not traditionally been used since it requires a complete redesign of the microcontroller system, particularly the SRAM structures. The Archimedes device includes custom SRAM arrays capable of robust operation below 0.4V. New technology advances, like these custom SRAM arrays, have only recently made possible the commercial roll-out of an aggressively voltage- scaled design. Next-generation microcontrollers using aggressive voltage scaling will enable dramatic active mode energy reductions.
Fig 4: Active energy consumption as a function of supply voltage in the Archimedes microcontroller.
In addition to a focus on active mode energy, Archimedes includes a wide range of techniques to address sleep mode energy, a particular challenge for today’s microcontrollers. The Cortex-M3 architecture enables sleep mode energy reductions since it supports sleep modes in which unused components can be power gated. The Archimedes device includes components that are entirely power gated, partially gated, or ungated in sleep mode, as shown in figure 3. Most commercial microcontrollers today support various sleep modes in the same way.
However, architectural support for sleep modes is insufficient alone. While microcontrollers can achieve energy efficiency by power gating all components in the deepest sleep modes, such a mode is not practically useful to the microcontroller user. These deep sleep modes can only be exited by pulsing the reset signal, which generally requires that some other chip at the board level be active.
We introduce the concept of a more useful functional sleep mode in which components like SRAM, timers, and brown-out detect circuits remain active. It is vital that these components be implemented with energy-efficient circuit designs. The availability of extremely energy-efficient functional sleep modes will be critical tool for microcontroller users looking to improve power consumption.
The Archimedes microcontroller includes a custom 3kB retentive SRAM array that consumes only 3.3fW per bit or approximately 80pW for the entire array at 0.4V. Along with a custom sleep timer with special low power design, wake-up controller, and custom voltage converter with special low power design, the entire chip consumes only 550pW in a functional sleep mode. These power numbers are approximately 1000 times better than those of the leading low power microcontrollers today. While Archimedes is a research prototype not ready for commercial roll-out, it clearly shows that next-generation microcontrollers have room for significant improvement over today’s devices.