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A quad-pipelined 16/32-bit microcontroller core
1/9/2012 12:59 PM EST
The DQ80251 is a quad-pipelined ultra-high performance, speed optimized soft core, of a 16-bit/32-bit embedded microcontroller which has has been designed with a special concern for performance to power consumption ratio. This ratio is extended by an advanced power management PMU unit.
Digital Core Design (DCD) has 11 years of experience with 8051 architectures and the DQ80251 soft core is 100 percent binary-compatible with the industry standard 16-bit 80C251 and 8-bit 80C51 microcontrollers.
There are two working modes of the DQ80251: BINARY (where original 80C51 compiled code is executed) and SOURCE (native 80C251 mode, using all DQ80251 performance).
It has a built-in, configurable DoCD-JTAG on chip debugger, supporting Keil DK251 and standalone DoCD debug software. The Dhrystone 2.1 benchmark program runs 56.8 times faster than the original 80C51 and 4.81 times faster, than the original 80C251 at the same frequency.
This performance can be also exploited to great advantage in low power applications, where the core can be clocked over fifty times slower, than the original implementation, for no performance penalty. Additionally, compiled code size for SOURCE mode is about 2 times smaller, comparing to identical standard 8051 code, since DQ80251 instructions are more effective.
The DQ80251 is delivered with fully automated testbench and complete set of tests, easing package validation, at each stage of SoC design flow.
The CPU runs at up to 53.411 VAX MIPS at 100 MHz, has up to 8M bytes of program memory, up to 32k bytes of internal (on-chip) data memory, supports up to 8M bytes of external (off-chip) data memory, has up to 16 MB of total memory space for CODE and DATA, and has 32k bytes of extended stack space.
It provides user programmable program memory wait states solution for wide range of memories speed and user programmable extended data memory wait states solution for wide range of memory speeds.
A de-multiplexed address/data bus eases connection to memory and full program memory writes are supported. There is an interface for additional special function registers and the fully synthesizable, static synchronous design provides positive edge clocking and no internal tristates.
Table 1 gives a survey about the core area and performance in ASICs devices.
Core performance in ASIC devices – results given for working system with connected CODE and DATA memories. DoCD debugger increases core size about 3000 gates.
Dhrystone Benchmark Version 2.1 was used to measure core performance. Table 2 and figure 1 provide illustrations of the DQ80251 performance, in terms of VAX MIPS per 1 MHz rating.
Table 2: Core performance.
Figure 1: The DQ80251 performance, in terms of VAX MIPS per 1 MHz rating.
The peripherals :
● DoCD debug unit
DELIVERABLES
♦ Source code:
♦ Example application
♦ Technical support
Single Site license option – it is dedicated for small and middle sized companies, running their business at one location.
Multi Sites license option – it is dedicated for corporate customers, running their business at several places. Licensed product can be used in selected company branches. In all cases, number of IP Core instantiation within a project and number of manufactured chips are unlimited. The license is royalty-per-chip free. There is no restrictions regarding the time of use.
There are two formats of delivered IP Core
Up to 104 external (user) special function registers (ESFRs) may be added to the DQ80251 design. ESFRs are memory mapped into Direct Memory between addresses 0x80 and 0xFF, in the same manner as core SFRs and may occupy any address, that is not occupied by a core SFR.
The DQ80251 soft core is dedicated for operation with a range of program and data memories. Slow program and extended data memory may assert a memory WAIT signals, to hold up CPU activity for required period of time.
The pin descriptions are shown in table 3.
Table 3: Pin descriptions.
Fig 2: Details of the symbols used.
Figure 3 shows a block diagram of the core.
Figure 3: Block diagram of the DQ80251.
A 16/32-bit Arithmetic Logic Unit performs the arithmetic and logic operations, during execu-tion of an instruction. It contains accumulator (ACC), Program Status Word (PSW, PSW1), (B) registers and related logic, such as arithmetic unit, logic unit, multiplier and divider. The REGFILE – Contains complete set of 80251 dedicated: 8-bit {R0, R1, ..., R15} registers, 16-bit {WR0, WR2, ..., WR30} and 32-bit {DR0, DR4, ..., DR28, DR56, DR60} registers.
Opcode Decoder – Performs an opcode decoding instruction and control functions for all other blocks.
Control Unit – Performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and it manages the execution of all microcontroller tasks.
Program Memory Interface – Contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory (CODE) can be also written. Program fetch cycle length can be programmed by user. This feature is called Program Memory Wait States and allows core to work with different speed program memories. It works with synchronous or asynchronous memories.
EDATA Memory Interface - Contains memory access related registers. It performs the Extended Data Memory (EDATA) addressing and data transfers. EDATA read/write cycle length can be programmed by user. EDATA covers also XDATA space from 80C51. This feature is called EDATA Memory Wait States and allows core to work with different speed memories. It is fully configurable. It works with synchronous or asynchronous memories.
Internal Data Memory Interface – Internal Data Memory interface controls access into the whole 32kB of IDATA memory. It contains 16-bit Stack Pointer (SP) register and related logic. It is fully configurable from 1 kB to 32 kB.
SFRs Interface – Special Function Registers inter-face controls access to the special registers. It contains standard and used defined registers and related logic. All SFR registers are bit addressable. User defined external devices, can be quickly accessed (read, written, modified), by using all direct addressing mode instructions.
Interrupt Controller – Four Levels interrupt control module is responsible for the interrupt manage system, for external and internal interrupt sources. It contains interrupt related registers, such as Interrupt Enable (IE), Interrupt Priority (IPH, IPL) and (TCON) registers. Its upgraded version can be extended by extra user's dedicated interrupt sources. Interrupt vectors locations and spacing are fully configurable.
Timers – System timers module. Contains two 16bits configurable timers: Timer 0(TH0, TL0), Tim-er 1(TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 (or 4) CLK periods, when appropriate timer is enabled. In the counter mode, the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock source for UARTs.
UART0 – Universal Asynchronous Receiver and Transmitter module is full duplex, which means, that it can transmit and receive concurrently. Includes Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning, it can commence reception of the second byte, before the previously received byte has been read from the receive register. Writing to SBUF0 loads the transmit register and reading SBUF0, reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be synchronized by Timer 1 or Timer 2 (if present in system).
Ports - Block contains 8051 general purpose I/O ports. Each of ports pin can be read/write as a single bit or as a 8-bit bus P0, P1, P2, P3
Power Management Unit – contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode), to significantly reduce power consumption. Switchback feature allows UARTs and interrupts to be processed in full speed mode, if enabled. It's highly desirable, when microcontroller is planned to be used in portable and power critical applications.
DoCD Debug Unit – a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCD provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external data, program memories and all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, REGFILE and also on SFRs. Hardware breakpoint is executed, if any write/read occurs at particular address, with certain data pattern or without pattern. Two additional pins - CODERUN and DEBUGACS, indicate the state of the debugger and CPU. CODERUN is active, when CPU is executing an instruction. DEBUGACS pin is active, when any access is performed by DoCD debugger. The DoCD system includes JTAG interface and complete set of tools, to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.
Program memory space
The program memory space begins at address0x800000 and ends at 0xFFFFFF address. It gives8MB of code memory. The 64kB memory area, ranged 0xFF0000 to 0xFFFFFF, is intended for MCU51 compatible code. After each reset, the CPU starts execution in the program memory, at location 0xFF0000. Each interrupt has its own start address for its service routine. The interrupt vectors are also mapped, starting at 0xFF0000 location. This shown in figure 4.
Fig 4: Mapping of the the interrupt vectors.
Data memory
The DQ80251 has up to 32k bytes of internal data memory (IDATA) and up to 8MB of extended data memory (EDATA). This is shown in figure 5.
Fig 5: Memory map.
The lower internal RAM consists of four register banks, with eight registers each. The current bank is selected by PSW register. A bit addressable segment is mapped in range 0x20 to 0xFF and covers part of internal RAM and all SFR area. With the 16-, 24-bit direct or indirect addressing mode, 0x80 to 0xFF range of the internal memory is addressed.
With the 8-bit direct addressing mode, range 0x80 to 0xFF the SFR memory area, is accessed. Extended RAM space begins just after end of Internal RAM memory chip. For example, if internal RAM has 1kB size, then extended RAM starts at 1 kB address.
Digital Core Design
---------------------------------------------------------------
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You can also get a weekly newsletter highlighting the latest developments in this sector - just Click Here to request this newsletter using the Manage Newsletters tab - if you aren't already a member you'll be asked to register.
Digital Core Design (DCD) has 11 years of experience with 8051 architectures and the DQ80251 soft core is 100 percent binary-compatible with the industry standard 16-bit 80C251 and 8-bit 80C51 microcontrollers.
There are two working modes of the DQ80251: BINARY (where original 80C51 compiled code is executed) and SOURCE (native 80C251 mode, using all DQ80251 performance).
It has a built-in, configurable DoCD-JTAG on chip debugger, supporting Keil DK251 and standalone DoCD debug software. The Dhrystone 2.1 benchmark program runs 56.8 times faster than the original 80C51 and 4.81 times faster, than the original 80C251 at the same frequency.
This performance can be also exploited to great advantage in low power applications, where the core can be clocked over fifty times slower, than the original implementation, for no performance penalty. Additionally, compiled code size for SOURCE mode is about 2 times smaller, comparing to identical standard 8051 code, since DQ80251 instructions are more effective.
The DQ80251 is delivered with fully automated testbench and complete set of tests, easing package validation, at each stage of SoC design flow.
The CPU runs at up to 53.411 VAX MIPS at 100 MHz, has up to 8M bytes of program memory, up to 32k bytes of internal (on-chip) data memory, supports up to 8M bytes of external (off-chip) data memory, has up to 16 MB of total memory space for CODE and DATA, and has 32k bytes of extended stack space.
It provides user programmable program memory wait states solution for wide range of memories speed and user programmable extended data memory wait states solution for wide range of memory speeds.
A de-multiplexed address/data bus eases connection to memory and full program memory writes are supported. There is an interface for additional special function registers and the fully synthesizable, static synchronous design provides positive edge clocking and no internal tristates.
Table 1 gives a survey about the core area and performance in ASICs devices.
Table 1: Core area and performance.
Core performance in ASIC devices – results given for working system with connected CODE and DATA memories. DoCD debugger increases core size about 3000 gates.
Dhrystone Benchmark Version 2.1 was used to measure core performance. Table 2 and figure 1 provide illustrations of the DQ80251 performance, in terms of VAX MIPS per 1 MHz rating.
Table 2: Core performance.
Figure 1: The DQ80251 performance, in terms of VAX MIPS per 1 MHz rating.
● DoCD debug unit
- Processor execution control
- Run, Halt
- Step into instruction
- Skip instruction
- Read-write all processor contents
- Program Counter (PC)
- Program Memory
- Internal (direct) Data Memory
- Special Function Registers (SFRs)
- Extended Data Memory
- Code execution breakpoints
- Two real-time PC breakpoint
- Unlimited number of real-time OPCODE breakpoints
- Hardware execution watch-points at
- Internal Data Memory
- Extended Data Memory
- Special Function Registers (SFRs)
- Hardware watch-points activated at a certain
- Address by any write into memory
- Address by any read from memory
- Address by write into memory a required data
- Address by read from memory a required data
- Automatic adjustment of debug data transfer
- Speed rate between HAD and Silicon
- JTAG Communication interface
- Power management mode
- Switchback feature
- Stop mode
- 4 priority levels
- 2 external interrupt sources
- 3 interrupt sources from peripherals
- Bit addressable data direction for each line
- Read/write of single line and 8-bit group
- Timers clocked by internal source
- Auto reload 8-bit timers
- Externally gated event counters
- Synchronous mode, fixed baud rate
- 8-bit asynchronous mode, fixed baud rate
- 9-bit asynchronous mode, fixed baud rate
- 9-bit asynchronous mode, variable baud rate
- Program Memory size: 64kB - 8MB
- Internal Data Memory size: 1kB - 32kB
- Extended Data Memory size: 1kB - 8MB:
- Program Memory Interface: synchronous & asynchronous
- Data Memory Interface: synchronous & asynchronous
- Interrupts: subroutines location
- Power Management Mode: used & unused
- Stop mode: used & unused
- DoCD debug unit: used & unused.
DELIVERABLES
♦ Source code:
- VERILOG Source Code or/and
- VHDL Source Code or/and
- FPGA Netlist
- NCSim automatic simulation macros
- ModelSim automatic simulation macros
- Active-HDL automatic simulation macros
- Tests with reference responses
- Installation notes
- HDL core specification
- Datasheet
♦ Example application
♦ Technical support
- IP Core implementation support
- 3 months maintenance
- Delivery the IP Core updates, minor and major versions changes
- Delivery the documentation updates
- Phone & email support
Single Site license option – it is dedicated for small and middle sized companies, running their business at one location.
Multi Sites license option – it is dedicated for corporate customers, running their business at several places. Licensed product can be used in selected company branches. In all cases, number of IP Core instantiation within a project and number of manufactured chips are unlimited. The license is royalty-per-chip free. There is no restrictions regarding the time of use.
There are two formats of delivered IP Core
- VHDL, Verilog RTL synthesizable source code called HDL Source
- FPGA EDIF/NGO/NGD/QXP/VQM called Netlist
Up to 104 external (user) special function registers (ESFRs) may be added to the DQ80251 design. ESFRs are memory mapped into Direct Memory between addresses 0x80 and 0xFF, in the same manner as core SFRs and may occupy any address, that is not occupied by a core SFR.
The DQ80251 soft core is dedicated for operation with a range of program and data memories. Slow program and extended data memory may assert a memory WAIT signals, to hold up CPU activity for required period of time.
The pin descriptions are shown in table 3.
Table 3: Pin descriptions.
Fig 2: Details of the symbols used.
Figure 3 shows a block diagram of the core.
Figure 3: Block diagram of the DQ80251.
A 16/32-bit Arithmetic Logic Unit performs the arithmetic and logic operations, during execu-tion of an instruction. It contains accumulator (ACC), Program Status Word (PSW, PSW1), (B) registers and related logic, such as arithmetic unit, logic unit, multiplier and divider. The REGFILE – Contains complete set of 80251 dedicated: 8-bit {R0, R1, ..., R15} registers, 16-bit {WR0, WR2, ..., WR30} and 32-bit {DR0, DR4, ..., DR28, DR56, DR60} registers.
Opcode Decoder – Performs an opcode decoding instruction and control functions for all other blocks.
Control Unit – Performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and it manages the execution of all microcontroller tasks.
Program Memory Interface – Contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory (CODE) can be also written. Program fetch cycle length can be programmed by user. This feature is called Program Memory Wait States and allows core to work with different speed program memories. It works with synchronous or asynchronous memories.
EDATA Memory Interface - Contains memory access related registers. It performs the Extended Data Memory (EDATA) addressing and data transfers. EDATA read/write cycle length can be programmed by user. EDATA covers also XDATA space from 80C51. This feature is called EDATA Memory Wait States and allows core to work with different speed memories. It is fully configurable. It works with synchronous or asynchronous memories.
Internal Data Memory Interface – Internal Data Memory interface controls access into the whole 32kB of IDATA memory. It contains 16-bit Stack Pointer (SP) register and related logic. It is fully configurable from 1 kB to 32 kB.
SFRs Interface – Special Function Registers inter-face controls access to the special registers. It contains standard and used defined registers and related logic. All SFR registers are bit addressable. User defined external devices, can be quickly accessed (read, written, modified), by using all direct addressing mode instructions.
Interrupt Controller – Four Levels interrupt control module is responsible for the interrupt manage system, for external and internal interrupt sources. It contains interrupt related registers, such as Interrupt Enable (IE), Interrupt Priority (IPH, IPL) and (TCON) registers. Its upgraded version can be extended by extra user's dedicated interrupt sources. Interrupt vectors locations and spacing are fully configurable.
Timers – System timers module. Contains two 16bits configurable timers: Timer 0(TH0, TL0), Tim-er 1(TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 (or 4) CLK periods, when appropriate timer is enabled. In the counter mode, the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock source for UARTs.
UART0 – Universal Asynchronous Receiver and Transmitter module is full duplex, which means, that it can transmit and receive concurrently. Includes Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning, it can commence reception of the second byte, before the previously received byte has been read from the receive register. Writing to SBUF0 loads the transmit register and reading SBUF0, reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be synchronized by Timer 1 or Timer 2 (if present in system).
Ports - Block contains 8051 general purpose I/O ports. Each of ports pin can be read/write as a single bit or as a 8-bit bus P0, P1, P2, P3
Power Management Unit – contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode), to significantly reduce power consumption. Switchback feature allows UARTs and interrupts to be processed in full speed mode, if enabled. It's highly desirable, when microcontroller is planned to be used in portable and power critical applications.
DoCD Debug Unit – a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCD provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external data, program memories and all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, REGFILE and also on SFRs. Hardware breakpoint is executed, if any write/read occurs at particular address, with certain data pattern or without pattern. Two additional pins - CODERUN and DEBUGACS, indicate the state of the debugger and CPU. CODERUN is active, when CPU is executing an instruction. DEBUGACS pin is active, when any access is performed by DoCD debugger. The DoCD system includes JTAG interface and complete set of tools, to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.
Program memory space
The program memory space begins at address0x800000 and ends at 0xFFFFFF address. It gives8MB of code memory. The 64kB memory area, ranged 0xFF0000 to 0xFFFFFF, is intended for MCU51 compatible code. After each reset, the CPU starts execution in the program memory, at location 0xFF0000. Each interrupt has its own start address for its service routine. The interrupt vectors are also mapped, starting at 0xFF0000 location. This shown in figure 4.
Fig 4: Mapping of the the interrupt vectors.
Data memory
The DQ80251 has up to 32k bytes of internal data memory (IDATA) and up to 8MB of extended data memory (EDATA). This is shown in figure 5.
Fig 5: Memory map.
The lower internal RAM consists of four register banks, with eight registers each. The current bank is selected by PSW register. A bit addressable segment is mapped in range 0x20 to 0xFF and covers part of internal RAM and all SFR area. With the 16-, 24-bit direct or indirect addressing mode, 0x80 to 0xFF range of the internal memory is addressed.
With the 8-bit direct addressing mode, range 0x80 to 0xFF the SFR memory area, is accessed. Extended RAM space begins just after end of Internal RAM memory chip. For example, if internal RAM has 1kB size, then extended RAM starts at 1 kB address.
Digital Core Design
---------------------------------------------------------------
If you found this article to be of interest, visit the Micocontroller Designline where you will find links to relevant technical articles, blogs, new products and news.
You can also get a weekly newsletter highlighting the latest developments in this sector - just Click Here to request this newsletter using the Manage Newsletters tab - if you aren't already a member you'll be asked to register.
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