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Road to ARM TechCon: Cortex-A9 Processor Optimization Pack
Rahoul Varma, ARM
10/15/2012 5:00 PM EDT
More POP
All cells within the base library, HPK and PMK have the flexibility to co-exist in the same standard cell row as part of the same block or design. The standard cell architecture allows ease of implementation without the requirement to partition the physical implementation or the need to add further implementation complexity. ARM also offers an ECO kit library that can also co-exist within the same standard cell design. ECO cells are embedded as filler cells and can be programmed (by mask layers) later to provide different functions as required.
The Fast Cache Instances (FCIs) provided in the POP are carefully tailored and customized for Cortex-A9, so there is a close balance of setup and access time with the requirements of the Cortex-A9 design. ARM has gone through a careful process to manually optimize and tailor the setup and access times of the memories, so that clock frequency is not limited by the memory-related timing paths.
ARM Implementation Benchmarking
Designers generally target worst-case conditions during system-on-chip (SoC) design, with some margin to allow for manufacturing variation in the silicon fabrication process. Variation is split into several variables: process, voltage and temperature. The process variation accounts for different thicknesses in metals or transistor layers that can make the design appear slower or faster. The variation of voltage is needed to account for voltage drop between the power supply and the transistor devices embedded in your SoC. Finally, the variation in temperature allows different operating conditions; for instance, ensuring the device will continue to operate in high temperatures or in sub-zero conditions.
ARM carries out all benchmarking under multiple conditions – from worst case conditions with pessimistic margins and typical conditions; allowing ARM to be credible with its performance results. It ensures that a partner will be able to re-produce the worst-case results and potentially improve the metrics further by using different margins, optimizations and conditions as appropriate for their end application.
Each benchmark carried out with the POP Physical IP components goes through several different areas of exploration mainly related to tuning the physical implementation and using flow optimizations. ARM engineers run dozens of implementation trials exploring a broad and complex range of design variables including core configurations, operating conditions and process variations. The work done by our POP team allows partners to take advantage of ARM’s performance exploration; output from most of the trials is documented in the user guide. ARM is able to take advantage of its knowledge in the Cortex-A processors and Physical IP libraries to tune the performance and power results.
The benchmarking core configuration is extremely important. ARM appreciates that a uni-core (single CPU configuration) can run incrementally faster than a dual-core processor implementation. Through market trends, ARM understands that the minimum specification for a number of applications is a dual-core Cortex-A9, and to gain the best system performance, it is important that the L1 processor (Cortex-A series) is coupled with a L2 cache controller and clocked at the same frequency as the L1 sub-system. Clocking the L2 controller at the CPU clock rate minimizes the L1 to L2 latency, making it essential for POP development to include the entire L1/L2 sub-system as part of the implementation benchmarking activity.
Going further, ARM has several different optimization targets for the implementation -- from maximum performance to power optimized. This allows the customer to select the optimization point that is best suited to the design goal and make the appropriate trade-offs. Figure 2 below shows how the same POP components can be targeted to achieve multiple optimization points.
Next: Knowledge Transfer
All cells within the base library, HPK and PMK have the flexibility to co-exist in the same standard cell row as part of the same block or design. The standard cell architecture allows ease of implementation without the requirement to partition the physical implementation or the need to add further implementation complexity. ARM also offers an ECO kit library that can also co-exist within the same standard cell design. ECO cells are embedded as filler cells and can be programmed (by mask layers) later to provide different functions as required.
The Fast Cache Instances (FCIs) provided in the POP are carefully tailored and customized for Cortex-A9, so there is a close balance of setup and access time with the requirements of the Cortex-A9 design. ARM has gone through a careful process to manually optimize and tailor the setup and access times of the memories, so that clock frequency is not limited by the memory-related timing paths.
ARM Implementation Benchmarking
Designers generally target worst-case conditions during system-on-chip (SoC) design, with some margin to allow for manufacturing variation in the silicon fabrication process. Variation is split into several variables: process, voltage and temperature. The process variation accounts for different thicknesses in metals or transistor layers that can make the design appear slower or faster. The variation of voltage is needed to account for voltage drop between the power supply and the transistor devices embedded in your SoC. Finally, the variation in temperature allows different operating conditions; for instance, ensuring the device will continue to operate in high temperatures or in sub-zero conditions.
ARM carries out all benchmarking under multiple conditions – from worst case conditions with pessimistic margins and typical conditions; allowing ARM to be credible with its performance results. It ensures that a partner will be able to re-produce the worst-case results and potentially improve the metrics further by using different margins, optimizations and conditions as appropriate for their end application.
Each benchmark carried out with the POP Physical IP components goes through several different areas of exploration mainly related to tuning the physical implementation and using flow optimizations. ARM engineers run dozens of implementation trials exploring a broad and complex range of design variables including core configurations, operating conditions and process variations. The work done by our POP team allows partners to take advantage of ARM’s performance exploration; output from most of the trials is documented in the user guide. ARM is able to take advantage of its knowledge in the Cortex-A processors and Physical IP libraries to tune the performance and power results.
The benchmarking core configuration is extremely important. ARM appreciates that a uni-core (single CPU configuration) can run incrementally faster than a dual-core processor implementation. Through market trends, ARM understands that the minimum specification for a number of applications is a dual-core Cortex-A9, and to gain the best system performance, it is important that the L1 processor (Cortex-A series) is coupled with a L2 cache controller and clocked at the same frequency as the L1 sub-system. Clocking the L2 controller at the CPU clock rate minimizes the L1 to L2 latency, making it essential for POP development to include the entire L1/L2 sub-system as part of the implementation benchmarking activity.
Going further, ARM has several different optimization targets for the implementation -- from maximum performance to power optimized. This allows the customer to select the optimization point that is best suited to the design goal and make the appropriate trade-offs. Figure 2 below shows how the same POP components can be targeted to achieve multiple optimization points.
Next: Knowledge Transfer
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