The OpenRISC project was started in 1999 by a group of Slovenian university students. Their aim was to create an open source microprocessor architecture specification and implementation. Two years later, they had produced a complete architectural specification, architectural simulator, and Verilog HDL implementation and made everything publicly available through their new open hardware community, OpenCores.
The OpenRISC 1200 (OR2100) is a synthesizable CPU core maintained by the developers at OpenCores.org. The OR1200 design is an open source implementation of the OpenRISC 1000 RISC architecture. The Verilog RTL description is released under the GNU Lesser General Public License (LGPL).
- Everything is open source. RTL source code is available.
- The ORPSoC reference platform makes it easy to implement an OpenRISC system
- The GNU toolchain is fully supported
- A large user community can help solve problems
- Few FPGA development boards are supported
- Complicated debug solutions
- The Wishbone bus is somewhat outdated
- The OpenCores website is confusing
- Many IP blocks are not maintained
Using the OpenRISC 1200 soft-core processor is a mixed bag. It is hard to find the way through the OpenCores website and there is no obvious starting point for a newbie. But after finding and downloading the hardware and software support files, it is rather easy to build a system and install Linux if choosing the right FPGA development board.
to check out the entire OpenRISC-based design process in my blog.