Design Article
Four soft-core processors for embedded systems
Sven-Ake Andersson, Realtime Embedded
1/8/2013 3:23 PM EST
The Nios II
The Nios II is a proprietary 32-bit RISC architecture processor core developed by Altera for use in their FPGAs. The soft-core nature of the Nios II processor lets the system designer specify and generate a custom Nios II core, tailored for his or her specific application requirements. System designers can extend the Nios II's basic functionality by adding a predefined memory management unit and/or defining custom instructions and custom peripherals.
Pros
Cons
Summary
The Altera Quartus II and Nios II Embedded Design Suite make it very easy to build a NIOS II-based system and to write application software that will run on this system. The complete Nios II system is specified in the Qsys tool where the processor is configured and all other system components are added.
More information
Click Here to check out the entire Nios II-based design process in my blog.
Next: Performance measurements
The Nios II is a proprietary 32-bit RISC architecture processor core developed by Altera for use in their FPGAs. The soft-core nature of the Nios II processor lets the system designer specify and generate a custom Nios II core, tailored for his or her specific application requirements. System designers can extend the Nios II's basic functionality by adding a predefined memory management unit and/or defining custom instructions and custom peripherals.
Pros
- Easy-to-use development environment
- No license required for building a system when using the Quartus II Web Edition
- No extra JTAG programming tool needed
Cons
- Can only be used in Altera FPGAs
- Some IP cores have time-limited licenses that will stop working after some time. They will continue to work as long as the development board is connected to your host computer.
Summary
The Altera Quartus II and Nios II Embedded Design Suite make it very easy to build a NIOS II-based system and to write application software that will run on this system. The complete Nios II system is specified in the Qsys tool where the processor is configured and all other system components are added.
More information
Click Here to check out the entire Nios II-based design process in my blog.
Next: Performance measurements
|
|
|
|
|
Navigate to related information
iniewski
1/9/2013 11:51 AM EST
Interesting article Sven...would you be interested in expanding it to a book chapter for the embedded system book I am editing? kris.iniewski@gmail.com
Sign in to Reply
green_is_now
1/10/2013 5:43 PM EST
You forgot at least one company
Micro-Semi-Actel SmartFusion ARM single Hard core
Probably the lowest power consumption/bit.
but have not checked specs recently.
Zync is impressive...I want a platform, just because of the raw potential.
Sign in to Reply
Alxx123
1/15/2013 1:02 AM EST
The parallella boards are a cheap way to get a zynq board - $99
http://www.adapteva.com/products/eval-kits/parallella/
Sign in to Reply
Weatherbee
1/12/2013 11:50 AM EST
First off, being a hardware guy let me say that I love FPGAs. I've had a really difficult time though justifying them for any but the absolute highest end special purpose commercial purposes. I think it is valuable to point out that both hard macro and soft core microprocessors still require external DRAM hanging off of the FPGA to implement a practical soft core processor that can say boot Linux. Does this really make it practical to freely synthesize additional cores after the chip level hardware is locked down? The entire for/against argument changes when you consider synthesizing microcontrollers that use the FPGAs integrated block rams.
Secondly, and I think this is the most important point. FPGAs are just expensive. I'd honestly like to see a table constructed showing say these four soft core processors and calculating based on FPGA cost in similar quantities to standalone uP, logic cells consumed and execution performance a cost in dollars per CoreMark or DMIP.
Even the hard macro based FPGAs seem to be quite pricey (take an honest look at Zync, Fusion and whatever Altera is calling their thing now). Also consider that in nearly every case the hard macro peripheral support is totally inferior to a modern uP SOC. Something like CAN or Gig Ethernet, video/graphic accelerators etc. are outrageously expensive to synthesize in these EPP type devices.
For prototyping SOCs I see the picture. As a very specialized PCIe attached coprocessor for your signal processing application or to implement custom high speed logic I see it. But I just don't the value proposition when it comes to replacing the function of a dsp or microprocessor in designs that by their very nature (using FPGAs) are custom already. There it is more of a hobby. Something that us engineers talk our employers into on really shaky arguments because we want to screw around with cool stuff. Show me that I'm wrong. Please!!!
Sign in to Reply
Weatherbee
1/12/2013 12:04 PM EST
BTW, I didn't mean to imply that SmartFusion was identical in application to Zynq or the Arria SOCs. Obviously the SmartFusion is a microcontroller and doesn't need external RAM, nor is it going to boot "real" Linux (though I don't think that is even a good criteria for this sort of thing). Not to mention that the Actel parts are based on an entirely different market space and value proposition where this hard processor + FPGA fabric thing may actually make some sense.
Sign in to Reply
Etmax
1/14/2013 7:18 PM EST
I agree on all counts, I've seen projects ruined on a cost basis because of "cool" ideas. Engineers should take a biological approach to design, ie. no dead weight to coin a phrase. A lot of these things are great "ideas", but the application has to need them.
Sign in to Reply