See Part 1 for an analysis of receiver performance specifications. See Part 3 for an analysis of issues in the transmit path, including frequency error and power control.
See Part 4 to learn about PA linearization.
See Part 5 for an an in-depth look at transmit modulation and direct conversion.

There are two ways of implementing the variable gain amplifier (VGA). For example, the VGA can be set to adjust signals at the bottom end of the range, reducing gain as soon as signals are large enough to overcome noise limitations. Likewise, the VGA can be set to adjust signals at the top end of the range, reducing the gain just prior to clipping or limiting within the signal chain. Each has advantages and disadvantages with a desirable goal being to implement the receiver without any gain control.

If a VGA is implemented, it should include both voltage and time hysteresis to prevent remodulation of signals. Table 1 shows expected sensitivity as gain is rolled off. It should be remembered that as gain is reduced, the analog-to-digital converter (ADC) contributes more to the total noise figure (NF) of the receiver and therefore overall receiver impairments. For example, in the high gain state, the noise density of the front end presented to the ADC is -131 dBm/Hz. In the low gain state, the noise has dropped to -137 dBm. If the ADC noise density is -145 dBm, the implication is an increase in the percentage of total noise that comes from the ADC. Given this, as long as sufficient gain can be run, a 14-bit converter is more than adequate for a multicarrier implementation of wideband CDMA (WCDMA). If conversion gain begins to run low, the noise of the ADC dominates and receiver performance suffers.

The required analog gain control can be implemented by taking advantage of the power measurement within the AD6636 or through other digital signal processing (DSP) calculations with the loop completed through a VGA implementation. In addition, the AD6636 incorporates an ADC preclip function that allows peak signals that are less than full scale to be detected and sets the gain of a digital gain amplifier or PIN diode attenuator before the converter full scale is reached, thereby preventing converter clipping.

The direct digital converter (DDC) also incorporates digital compensation for the analog changes so that the final digital data is relinearized with respect to the true analog input to the receiver. Similarly, the latency of the analog gain path, including the pipeline delay of the ADC, is accounted for in this process.

SFDR Requirements
Spurious performance is a little less obvious from the specifications. However, there are several guidelines in the 3GPP standard that provide SFDR requirements. These are primarily found in the single and two-tone blocking specifications. In this test, a narrow- band signal (CW) is allowed to intermodulate with either a WCDMA signal or a GMSK signal depending on the band of operation. For WCDMA conditions, both signals are posted at -48 dBm whereas the GMSK (bands II and III) are set to -47 dBm.

Looking first at the band II and III test with GMSK, the intermodulation product falls outside the channel of interest, 2.4 MHz from channel center where the channel 3 dB bandwidth is 1.92 MHz. Digital channel filtering provides adequate filtering of the intermodulation products before the correlator and, therefore, no direct impact is anticipated with the signal of interest. It is assumed that fifth order products are significantly better than anticipated third order products. Even though they fall inband, they should not be an issue. If they do, they must meet the spurious requirements determined below. For the intermodulation between a CW tone and a WCDMA carrier, the resulting intermodulation product falls directly on the channel of interest. The net effect of this is to increase the noise in the channel as would additive white Gaussian noise (AWGN).

The specification allows for 6 dB of reduced sensitivity for this test. Since receiver performance is limited by thermal noise, setting noise due to intermodulation and spurious equal to the noise floor increases the noise by 3 dB and reduces the sensitivity by the same amount. Since 6 dB is allowed, the remaining 3 dB can be allocated elsewhere (jitter, additional NF, or other). Assuming that conversion gain has not yet been reduced from 40 dB (the AGC point is above the two-tone levels) and that the ADC is providing 74 dB of SNR, the total NF of the receiver is 3.1 dB. Therefore, the noise density (reflected back to the antenna) including the ADC is -171 dBm/Hz. If this is integrated over one channel (3.84 MHz), the total noise is -105 dBm. This is the power of the intermodulation term that is allowed by the intermodulation between the CW and WCDMA signals. This provides detailed information about spurious levels that have to be met.

If the intermodulation product is a WCDMA-type product, the energy is already spread and simply appears as AWGN (and spread over 2x by convolution between two different codes—assuming that aliasing does not occur somewhere in the receiver chain). The only exception to this is, of course, if the intermodulating signal is not orthogonal to the signal of interest, but this is assumed not to be the case.

Similarly, if the IMD product is a CW tone (not specified in the standard, but is a worst case), it spreads by the PN sequence in the correlation process, again appearing as AWGN. Since all of the energy in a CW tone is within a single frequency, this is a more stringent test. Therefore, if the ADC input-referred spurious (the sum of all spurious) must be -65 dBm (-105 dBm plus 40 dB), this sets the absolute worst case spurious that can be tolerated for a co-channel interferer whether generated by single tone, multi-tone, or intermodulation. Since the ADC full scale is +4 dBm (rms) and the worst case equivalent sum of spur that can be tolerated is -65 dBm, this is equivalent to an SFDR of about 69 dBFS (decibels full scale) minimum. While conditions that generate the worst case may vary, this represents the worst case cumulative SFDR that can be tolerated.

SFDR Split
If it is assumed that the ADC and the down-converter block equally share in the harmonic distortions and are not correlated, each source should be no worse than -72 dBFS (relative to the ADC input) and, more appropriately, -78 dBFS which allows not only for headroom but for the case where the two contributions to SFDR can peak simultaneously.

For the case where the gain has been reduced to account for larger blockers (band II and III), the spurious requirements are higher. Although the details are not shown here, the cumulative SFDR is 75 dBFS and allowing for headroom and signal peaking, 81 dBFS minimum.

IP3 Requirements
One of the more stringent intermodulation tests are in band II and III under the GMSK test. In this case, two essentially narrow-band tones are placed into the receiver at -47 dBm. This would be the condition as anticipated in a mixed band. For band II and III, the third-order intercept (IP3) requirements are easy to predict.

For band I, where the intermodulation tones are a CW tone and another WCDMA signal, it is not as direct to compute, and in the end is less critical than the specified band II and III conditions. With two narrow-band tones on the antenna port and the gain not yet reduced, the required intermodulation products must be lower than -105 dBm at the antenna port as previously determined. With the inputs at -47 dBm, the required IP3 referenced to the antenna port is -18 dBm. Reflected to the ADC input, this is +22 dBm assuming a conversion gain of 40 dB.

Realistically, there can be other more stringent tests. In the case of a wideband (multicarrier) receiver architecture as proposed here, it is likely that signals as large as -30 dBm are processed by the analog section of the receiver, if only at the band edge. In this case, the numbers would need to be recomputed but would need to take into account the reduction of gain and the increase in system noise. From the ADC perspective, equivalent IP3 performance is in excess of +40 dBm and not a factor; therefore, IP3 is solely contributed from the downconverter block. In the case where higher conversion gain is used, IP3 requirements, as well as noise requirements, scale appropriately. Likewise, design specific margins increase the required performance above the minimums previously shown.

Component Selection
Based on the previous discussion, the downconversion block must have a conversion gain of about 40 dB, a noise figure of 3 dB, and an output IP3 of at least +22 dBm. Current receiver technology is capable of this level of performance. Furthermore, room exists to further enhance performance beyond the minimum performance shown here with little effort.

Synthesizer
A number of suitable synthesizers are available for this design. Figure 1 shows a design including the ADF4106 ultralow noise phase locked loops (PLLs) and the ADF4360-xfamily of integrated synthesizers and VCOs. The ADF4360 family of synthesizers is well suited for WCDMA Rx and Tx applications as proposed here.

ADC
As discussed in the previous sections, the converter needs an SNR of about 74 dBFS with a -3 dBFS input signal. For IF sampling, products such as the AD9446, AD9445, AD9444, and AD9246 are some of the latest announced devices.

For baseband sampling, the AD9238 and AD9248 dual, 12-bit and 14-bit converters are pin compatible and allow assembly options for platforms that may be common between single and multicarrier applications and where export/import restrictions may exist. In addition to these pin-compatible devices, new quad ADCs are available, including the AD9228 and AD9229. These quad, 12-bit converters are ideal for diversity baseband IQ sampling or for quad, low IF sampling applications such as phased array antennas.

Digital Downconverter (DDC) The AD6636 offers a 4-channel or 6-channel DDC option. Each of these devices has four ADC inputs and, therefore, is easily configured as either diversity, diversity sectored, or phased array. Two ADCs can drive one of these devices to form a diversity two-(4-channel) or three-(6-channel) carrier receiver.

One interesting configuration is shown in Figure 5. This application shows a three-sector, four-carrier antenna downconverted and digitized. The digitized signal is then passed to two different DDCs. Each DDC is then used to select and filter two frequency allocations (FAs) for a total of four FAs per sector. In addition to four diversity FAs per sector, this configuration provides redundancy in the event of a failure.

Since each antenna is routed to two DDCs, the failure of a DDC does not take out an entire channel. Likewise, the diversity antenna is routed to two different DDCs providing redundancy there as well. In addition, the diversity signal path is handled by a completely different signal path from the main, providing as much as a four-way redundancy for signal processing. Therefore, in the event of the failure of the main path, the diversity path is totally redundant and not effected by the main path failure. Using this architecture, each sector is 100% covered by redundancy (RF through channelization) in the receive path regardless of the loss. The system is not reliant on any one single component and has a high degree of ability to reallocate channel capacity to other DDCs, in the event of a failure or even increased traffic volume.

In addition to the channelization capabilities, other functions are provided in the DDCs. The first is power estimation. The mean square power, peak power, and the number of times the signal crosses a specified amplitude can be measured for each ADC input. Additionally, when used in complex mode (I and Q), these measurements are done on the complex signals as well. This information can be used in conjunction with attenuation in the front end to prevent overloading in case strong signals are detected. Additionally, each DDC channel has an rms power measurement function with programmable integration for flexibility. This function can be used to set receiver gain, determine loop loss, and generate a digital output AGC function to keep the digital output bits in a narrow dynamic range for use with low bit precision rake receivers.

Other key features include dc offset correction, IQ gain adjustment, IQ phase adjustment, and complex digital tuning. All of these features are required when implementing IQ sampling for multicarrier applications.

Integrated Functions
Currently, 14-bit ADCs are under export restriction to key countries. The AD6654 provides integration of the ADC and DDC function by combining the AD6645 and AD6636 cores in a single device. This device is classified as a receiver function and is not subject to export control. In addition to this, combined Rx functions are available that integrate both transmit and receive in a single package. Devices such as the AD9863 include dual, high speed ADCs and DACs suitable for single carrier applications. This device is an excellent option for low capacity systems.

Validation
As seen in the following simulator output, with a minimum sensitivity signal of -121 dBm on the input, this receiver supports an SNR of over 8 dB with a gain of 40 dB, more than enough to meet the requirements for a wide area BS. This sensitivity can be maintained up to a total inband power level of about "36 dBm at the antenna. Beyond this, the input must be attenuated to prevent overdriving the receiver chain. The easiest way to meet the specification is to insert an attenuator to reduce the input signal level at the input of the receiver. While 6 dB would be ideal, additional attenuation can be used as long as the end sensitivity meets the -115 dBm specification. This is the case under the alternate channel blocking test at -40 dBm.

Table 2 shows the resulting SNR when the conversion gain is changed allowing for modest increases in the NF. As seen, while the SNR changes slightly, it should be remembered that the desired signal level increases by 6 dB, thereby increasing SNR by 6 dB above that shown in the table.

Validation of SFDR sensitivity is a little more difficult. However, clearly for a linear system, CW testing is more stringent than testing with a WCDMA signal. Therefore, if a CW signal at the ADC input is driven to the ADC full scale of +4 dBm (-24 dBm CW at the antenna with 28 dB of conversion gain), worst case spurious should be better than 81 dB lower. WCDMA signals of equivalent peak power produce much lower spurious results due to the much lower spectral density and rms level of the stimulus signal.

Typical minimums of 14-bit converters are specified at 85 dB or better depending on frequency. If 83 dB minimum is used (2 dB above the required), this is a CW SFDR power level of -79 dBm. After the rake receiver, this produces a spectral density of -144.8 dBm/Hz at the ADC or at the antenna of -172.8 dBm/Hz, about 8 dB lower than thermal after accounting for front end thermal noise. Therefore, the total noise in the channel of interest is increased by less than 1 dB, reducing overall sensitivity during this condition to better than -118 dBm, leaving a 3 dB margin to meet the specification of -115 dBm. Since a CW signal was used to approximate the effects of the peak signal of a WCDMA waveform, it is expected that the actual rms power of a realistic waveform is to be as much as 12 dB lower, thus achieving significant improvements in the SFDR performance of the receive channel over that expected by a CW tone.

Noise Margin
Ideally, the basestation should seek to maintain a relatively low input level for each frequency allocation. Typically, this would be maintained somewhere between -60 dBm and -70 dBm depending on how the controller is programmed. Under these conditions, each carrier should have an SNR of around 60 dB providing excellent bit error rate (BER) without the need to engage the gain reduction from the automatic gain control (AGC) loop. However, to be compliant with the specification, the adjacent and first alternate channels must be considered for the case where they may be outside the control of the base station or where they become large for some unforeseen reason.

For this condition, the desired sensitivity is -115 dBm, indicating that the gain can be reduced by the AGC loop. The impairing signals consist of the alternate signal at +63 dBc (-52 dBm) and the first alternate at +75 dBc (-40 dBm). Since these signals have only one code of modulation, the peak to rms is about 3.5 dB, resulting in a peak power of -36 dBm, which is at the upper limit of the highest gain setting. Given signal chain variations and power from other inband signals, it is assumed that the gain is reduced to the 34 dB setting, increasing the NF to 6.25 dB. In this condition, the desired signal should be processed with an available channel SNR of about 10.88 dB, resulting in a low BER. As discussed earlier, the addition of spurious energy from the large first alternate signal should be near the thermal noise level and have little impact on signals at this increased level.

Part 3 will cover key performance issues in the transmit path.

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