Multicarrier WCDMA Feasibility, Part 2

See Part 1 for an analysis of receiver performance specifications. See Part 3 for an analysis of issues in the transmit path, including frequency error and power control.
See Part 4 to learn about PA linearization.
See Part 5 for an an in-depth look at transmit modulation and direct conversion.

There are two ways of implementing the variable gain amplifier (VGA). For example, the VGA can be set to adjust signals at the bottom end of the range, reducing gain as soon as signals are large enough to overcome noise limitations. Likewise, the VGA can be set to adjust signals at the top end of the range, reducing the gain just prior to clipping or limiting within the signal chain. Each has advantages and disadvantages with a desirable goal being to implement the receiver without any gain control.

If a VGA is implemented, it should include both voltage and time hysteresis to prevent remodulation of signals. Table 1 shows expected sensitivity as gain is rolled off. It should be remembered that as gain is reduced, the analog-to-digital converter (ADC) contributes more to the total noise figure (NF) of the receiver and therefore overall receiver impairments. For example, in the high gain state, the noise density of the front end presented to the ADC is -131 dBm/Hz. In the low gain state, the noise has dropped to -137 dBm. If the ADC noise density is -145 dBm, the implication is an increase in the percentage of total noise that comes from the ADC. Given this, as long as sufficient gain can be run, a 14-bit converter is more than adequate for a multicarrier implementation of wideband CDMA (WCDMA). If conversion gain begins to run low, the noise of the ADC dominates and receiver performance suffers.

The required analog gain control can be implemented by taking advantage of the power measurement within the AD6636 or through other digital signal processing (DSP) calculations with the loop completed through a VGA implementation. In addition, the AD6636 incorporates an ADC preclip function that allows peak signals that are less than full scale to be detected and sets the gain of a digital gain amplifier or PIN diode attenuator before the converter full scale is reached, thereby preventing converter clipping.

The direct digital converter (DDC) also incorporates digital compensation for the analog changes so that the final digital data is relinearized with respect to the true analog input to the receiver. Similarly, the latency of the analog gain path, including the pipeline delay of the ADC, is accounted for in this process.

SFDR Requirements
Spurious performance is a little less obvious from the specifications. However, there are several guidelines in the 3GPP standard that provide SFDR requirements. These are primarily found in the single and two-tone blocking specifications. In this test, a narrow- band signal (CW) is allowed to intermodulate with either a WCDMA signal or a GMSK signal depending on the band of operation. For WCDMA conditions, both signals are posted at -48 dBm whereas the GMSK (bands II and III) are set to -47 dBm.

Looking first at the band II and III test with GMSK, the intermodulation product falls outside the channel of interest, 2.4 MHz from channel center where the channel 3 dB bandwidth is 1.92 MHz. Digital channel filtering provides adequate filtering of the intermodulation products before the correlator and, therefore, no direct impact is anticipated with the signal of interest. It is assumed that fifth order products are significantly better than anticipated third order products. Even though they fall inband, they should not be an issue. If they do, they must meet the spurious requirements determined below.