Packaging options expand in RF power

What is often overlooked is the pivotal role packaging has played in this rapid evolution. More robust packaging technology has helped RF power IC makers support the higher frequencies and bandwidths today’s designers require. In addition, package suppliers have helped basestation designers meet growing market demands for lower cost systems.

Similarly, as system integration trends continue to advance, lighter weight packaging technologies have helped RF designers develop new layouts for tower mounted electronics. This article will take a look at general packaging trends for RF power ICs, review some of the tradeoffs inherent in today’s popular packaging options, and examine how recent advances are opening up new opportunities for RF designers to meet next generation design requirements.

Focus on cost
Over-molded packaging solutions offer far-and-away the most cost-effective packaging platform for RF power applications. Commonly used in a wide variety of power IC applications, this technology encapsulates the semiconductor IC in a polymeric material which acts as a dielectric insulator and protects the device against mechanical and environmental degradation, Figure 1. Over-molded packaging solutions offer the powerful cost advantage of mainstream high volume manufacturing processes and suppliers.

Figure 1: Basic structure of the overmolded package
(Click on image to enlarge)

Depending on the product and design, cost is typically quoted in fractions of a cent per lead including die and wire bonding. This represents up to an order of magnitude cost savings over traditional ceramic packaging technologies. As a result, over-molded packaging is widely used in lower power and/ or lower frequency devices, drivers and wideband transistor applications.

As performance requirements for power RF applications have skyrocketed in recent years, however, over-molded packaging’s inherent limitations have come into play. First, over-molded compounds exhibit a relatively high moisture-absorption rate. Since the mold compound must adhere to the die, the wire bonds, and the lead material, these packages are subject to a “popcorn” effect, when moisture collects and ultimately explodes during the next level assembly process, leading to device failure.

Moreover, unlike a ceramic package where the die sits in an air cavity, over-molded packaging material comes into direct contact with the die and bond wires. Since polymers exhibit a higher dielectric constant than air, an over-molded package will experience higher parasitic, resulting in lower power output and gain depending on the design and tolerance of the encapsulated die.

Designers can compensate for some of these effects through careful attention to device design, product layout and wire-bonding techniques, and in some cases designers have crafted over-molded solutions for extremely high frequency applications. But generally speaking, applications that exceed 2GHz, require a more tolerant packaging solution. Finally, while end product costs are low, tooling for over-molded solutions can present a significant expense.

High-power solutions
Over the past few decades, the escalating performance and reliability requirements of power-RF devices have demanded ceramic packages which combine a thermally and electrically conductive metal base with a ceramic ring that isolates the input and output leads. These air cavity packages offer higher electrical isolation for the silicon die than comparable over-molded packages and are especially well-suited for high-frequency, high power applications.

In addition, the ceramic package provides a high level of durability for high-temperature soldering during the assembly process. Given its wide acceptance across the industry, ceramic packages are now available in a wide range of designs from numerous established suppliers. Accordingly, it is not surprising that more than 90% of all high power/higher frequency RF device in use today come housed in a ceramic package.

For many years, these packages used a metal base comprised of a copper-tungsten alloy that is brazed to a metalized and plated ceramic ring via a high temperature brazing process, Figure 2.

Figure 2: Standard ceramijc packages fulfill many application requirements
(Click on image to enlarge)

More recently, packaging manufacturers have moved to a more thermally- efficient and cost-effective base comprised of a laminated structure of copper/copper-moly/copper. The ceramic base is then gold-plated to allow the die to be attached via a second high temperature process. A ceramic lid is often glued to the ceramic ring and input and output leads to provide environmental protection.

While these metal-ceramic packages have offered OEMs a proven, reliable solution for high performance RF devices, they also bring some distinct liabilities. First and foremost, in the increasingly competitive wireless infrastructure market is the inherent cost. The high-temperature-fired ceramic and brazed assembly process needed to form the air-cavity package is an expensive one.

Moreover, as part of the package-assembly process, entire parts must be plated to a common gold thickness, irrespective of the minimum requirement for downstream assembly. This process results in wasted materials and higher end product costs, particularly as the cost of gold has skyrocketed. As a result, in many cases a ceramic package can represent as much as one-half the total cost of a finished power-RF device.

As basestation designers continue to design for greater bandwidth, power, and frequency to meet rising customer demand, thermal efficiency has emerged as an increasing crucial gating factor in any RF packaging solution. Ideally, a full metal base offers an ideal ground plane and heat sink. Ceramic packages require coefficient of thermal expansion (CTE) matching to preclude cracking of the ceramic. This requirement limits use of very high thermal conductivity materials/flanges and as such significantly restricts design flexibility. Ultimately the inability to use high thermal conductivity materials such as copper can and will impact device performance.

Maximizing design flexibility
Over the past few years, an alternative option to over-molded and traditional ceramic packaging has emerged for designers using power RF ICs. Like a ceramic package, Liquid Crystal Polymer (LCP) packaging uses an air cavity structure to maximize electrical isolation of the silicon die. The technology is based on a strong, inert thermoplastic that is resistant to heat, moisture, corrosives, and solvents, and is non-flammable. From a performance standpoint it supports the use of a wide band of power levels and is capable of handling frequencies from L to V band.

LCP packaging uses an insert-injection molding process that combines a metal alloy leadframe with an LCP sidewall, Figure 3.

Figure 3: Structure of Liquid Crystal Polymer (LCP) packaging
(Click on image to enlarge)

Packages are then supplied with a mated/matching LCP lid. The packages are available with a wide variety of interchangeable base materials offering designers a broad range of materials for CTE matching and thermal management. Ranging from ceramic (LTCC and HTCC) and copper alloys and copper laminates to OFHC copper and diamond, these package base/flange materials offer designers thermal conductivity capabilities that range from 10 W/°K to 1000 W/°K. The technology allows the package designer a wide range of design latitude with cost consciousness in mind.

The package sidewall does not require a similar plating process or type than the flange as in legacy technologies. Rather, the modular approach allows a designer to use lower cost plating techniques between the package body and package base. For example, the use of noble metals (gold) can be reduced or eliminated in the wire bonding areas of the package (such as using NiPdAu or spot plating), while the base/flange can be plated with gold plating thicknesses friendly to the customers’ requirements for a Gold Tin or Gold Silicon eutectic die attach process.

The technology features a flat sealing surface from lid to package thereby reducing the epoxy cross sectional thickness between lid and package and conversely increasing the shear/adhesion strength of the lid to package interface. The LCP itself is one-third the dielectric of ceramic and supplies a designer with a fully matched CTE solution. In addition, the LCP approach displays a very low water absorption rate of 0.02% offering near-hermetic reliability. Packages can be built to most industry standard configurations including RF power outlines, quad flat packs (QFPs), quad flat no-leads (QFNs) and small-outline (SO) solutions.

The distinct advantage to the LCP approach is its tremendous design flexibility. Designers can select any of a wide range of thermally-enhanced interchangeable bases depending upon application requirements. This unique modular approach and the ability to tailor the technology’s CTE allows designers, for example, to use a copper flange and achieve a 15 to 25% reduction in thermal resistance over comparable ceramic/ metal alloy solutions. That, in turn, can translate into improved energy and thermal efficiency and lower power consumption in basestation designs.

Moreover, the LCP package manufacturing process is highly cost effective. Packages are molded around a leadframe in a multi-up format in an automated manufacturing process. The LCP is formulated to match the CTE of the copper leadframe; which is used in most applications to minimize stress and maximize package reliability. Prior to molding, the leadframes are coated with a moisture resistant polymer to effectively seal the leadframe to package body interface. This sealing process is used to address one of the major liabilities of over-molded package technologies and offer near hermetic reliability.

As an example, a new LCP-based air cavity package developed recently by ST Microelectronics for RF power transistors achieves junction-to-case thermal resistance (RTH) of 0.28°C/W. This represents an approximately 20% improvement over comparable ceramic packages according to the manufacturer. Lower thermal resistance improves heat removal from the die during operation, allowing the transistor to deliver increased gain and better output power. Moreover, the new package technology offers better reliability. ST Microelectronics reports mean-time-to-failure (MTTF) for devices in the new package as four times longer than those in comparable ceramic packages.

As an alternative packaging option, LCP combines many of the advantages of both over-molded and ceramic technologies. The technology offers similar levels of mechanical stability and moisture resistance as legacy ceramic packaging. The use of automated manufacturing and assembly processes ensures low cost and promises larger cost reductions as the technology evolves. Further, the technology’s highly modular structure offers engineers an unprecedented level of design flexibility as they attempt to come up with the optimal solution for their unique design requirements. By tooling the technology for a specific size and simply changing out the lead frame, OEMs can create a whole family of products at lower cost from a single injection mold.

The primary liability LCP users face is the absence of a proven track record. Unlike comparable ceramic and over-molded solutions, LCP technology has not been widely used for decades. But as OEMs move to 3G and 4G basestation designs, the inherent advantages of the technology are beginning to bring wider scale adoption.

Conclusion
Packaging clearly plays a crucial role in the performance of RF power ICs. Since RF power transistors represent one of the more expensive and ubiquitous components in a basestation design, packaging technology also plays a key role in end product cost. The development of a wider array of packaging options promises to offer equipment designers new opportunities to find the best solution to their particular application.

About the author
Jeff Crowder is senior mechanical design engineer at RJR Polymers, Inc.,, an advanced semiconductor-packaging company is Oakland, CA. Prior to joining RJR, Jeff was a senior mechanical engineer at HVVi Semiconductor where he performed thermal and mechanical finite element analysis to optimize package design and ensure reliability. Earlier he spent over 16 years at Motorola/Freescale in various roles related to packaging technology. Jeff earned an MS in mechanical engineering at Purdue and a BS in physics at the University of Wisconsin-River Falls.