Design Article
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MikiW
Scott NSC
Software defined radio: Don't talk to me about ENOBS (Part 1 of 2)
Scott Kulchycki, National Semiconductor Corp.
9/20/2010 11:49 AM EDT
Some key goals of next-generation communication systems are the ability to provide much higher data capacity and system re-configurability while also reducing power, board area, and cost. These competing requirements are forcing re-evaluation of the capability of traditional system architectures to address many market demands including:
These market trends can be elegantly and efficiently addressed by a new breed of wideband software-defined radio (SDR) solutions. Recent advances in analog-to- digital converter (ADC) technology (12 bits at 3.6-GSPS) have enabled the development of wide bandwidth SDR systems that can simultaneously process multiple channels at high input frequencies. With this new ADC capability, systems can be developed that digitize entire input frequency bands with high resolution, removing the need for multiple receive paths or expensive analog filtering. Instead, all of the channel filtering can be implemented in the digital domain, where it can be accomplished at much lower power, area and cost, and with much better performance (see Figure 1 and Figure 2). Moving signal processing into the digital domain also allows for easier programming and on-the-fly system parameter reconfiguration, yielding truly programmable (or software-defined) systems.
Check out the full text of Part 1 of this article here (no registration, no funny business, just a link to the article). This part outlines traditional hardware-defined radio solutions and a new software-defined radio solution. It also covers system performance concerns and what are traditional specs for ADC.
Part 2 will will detail the limitations of traditional specs for SDR, and which ones really matter. It will publish September 23rd.
- Increased number of received channels for additional data capacity and capability Increased programmability and re-configurability to reduce re-design costs and
- enable easy customization
- Reduced energy consumption to improve system reliability, address regional and
- global green initiatives, and reduce operating expense
- Reduced board area and solution bill-of-materials
These market trends can be elegantly and efficiently addressed by a new breed of wideband software-defined radio (SDR) solutions. Recent advances in analog-to- digital converter (ADC) technology (12 bits at 3.6-GSPS) have enabled the development of wide bandwidth SDR systems that can simultaneously process multiple channels at high input frequencies. With this new ADC capability, systems can be developed that digitize entire input frequency bands with high resolution, removing the need for multiple receive paths or expensive analog filtering. Instead, all of the channel filtering can be implemented in the digital domain, where it can be accomplished at much lower power, area and cost, and with much better performance (see Figure 1 and Figure 2). Moving signal processing into the digital domain also allows for easier programming and on-the-fly system parameter reconfiguration, yielding truly programmable (or software-defined) systems.
Check out the full text of Part 1 of this article here (no registration, no funny business, just a link to the article). This part outlines traditional hardware-defined radio solutions and a new software-defined radio solution. It also covers system performance concerns and what are traditional specs for ADC.
Part 2 will will detail the limitations of traditional specs for SDR, and which ones really matter. It will publish September 23rd.
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Frank Eory
9/20/2010 7:27 PM EDT
Interesting article Scott, and I look forward to Part 2.
It's true that digital radio designers are more interested in specs that are not typically quoted for ADCs. It would eliminate a lot of the guesswork if comms-oriented ADCs quoted perfomance data on parameters like IMD and NPR.
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Jayakumar
9/23/2010 3:41 AM EDT
Very interesting to read about this article and we will look forward to read part 2. Speed in which ADC samples is very important and the same define how close we are towards true SDR. Do we have FPGA fabric to handle 3.5 GSPS samples and create I and Q channel and perform other operations in it. It is clear that present generation DSP’s may not able to do, but if these ADC’s fit in PCI or PXI bus of INTEL processors then we might able crank some amount of computations. Still challenge is there the way we do signal processing in Digital Part. May be we need to look at Neural Network based algorithms and innovation to work with high speed data at one side and very low speed decisions at other side of network. I am keen on looking for part 2 of Scott and hope he does touches the above part. (jk@epigon.co.in)
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Pazhy
9/23/2010 4:11 PM EDT
Thanks for the article. A wideband ADC will also pick up wideband noise and interferers. This will reduce the dynamic range of the ADC.
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Jaspreet.Singh
9/23/2010 8:48 PM EDT
What is the power consumption and cost of the 12-bit 3.6 Gsps ADC ? I suspect it might still be too high to prohibit its use for commercial applications.
What do you folks think about the future trends? As far as my understanding goes, it might be a long time till we have low-cost low-power Gsps ADCs.
Good thing nonetheless is that there is growing awareness among academicians as well about the associated signal processing challenges posed by this ADC bottleneck. There have recently been efforts towards exploring design with extremely low-precision ADCs (1-4 buts), and also massively parallel time-interleaved ADCs that can provide higher resolution.
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Frank Eory
9/24/2010 1:38 PM EDT
Keep in mind SDR is still mostly a military thing -- it has a ways to go before it's cost-effective and low enough power for everyday commercial applications.
A product brief on National's website says 4.1 watts @ 1.9V in a 292 pin thermally enhanced BGA package. You're clearly not going to put that in a cell phone, but that's not the target market.
Scott, is this a continuous time sigma delta architecture? Can you tell us if it's CMOS, SiGE, or what?
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Scott NSC
9/27/2010 11:10 AM EDT
Hi Frank,
The new 12-bit ADCs use a folding and interpolating architecture and they are manufactured in a CMOS process.
Thanks,
Scott
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MikiW
1/28/2012 11:31 AM EST
Hi,
Where can I find the second part of the article?
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