The Stage and Script
The basic architecture of an M-PHY system is shown in Figure 2. Each LINK is made up of two SUBLINKs, containing one or more LANEs. A LANE is a unidirectional point-to-point differential serial connection between PINs, called a LINE, and connects an M-PHY transmitter and an M-PHY receiver. LANEs running in the same direction constitute a SUBLINK. Two SUBLINKs running in opposite directions, plus the additional management function, complete a LINK. Thus, the operation of the M-PHY interface is completely defined in the context of a protocol definition like DSI, CSI, UniPro, or DigRF which manage the LANE.
Figure 2: Architecture of the M-PHY LINK, made up of a LINE, LANE, and SUBLINKs and LANE Management (Source: MIPI Alliance
There are two fundamentally different types of M-PHY interfaces, denoted as Type-I and Type-II, depending on which signaling scheme is used. For low-speed operation, Type-I employs PWM (pulse width modulation) signaling, while a Type-II uses system-clock synchronous NRZ (non-return-to-zero) signaling. Type-II requires a shared reference clock between the two ends of the line. Type-I is able to operate with independent local clock references on each side of the link. Type-I and Type-II are not interoperable, but implementations may support both types of in order to enable hardware reuse, so one M-PHY specifications can service multiple applications and connections inside a mobile device.
The two modes are illustrated in Figure 3. For PWM signaling (Type-I), there are multiple GEARs (they can switch like gears in a transmission) to cover different speed ranges. The default (mandatory) GEAR for Type-I is PWM-G1, ranging from 3 to 9 Mbps. There are six GEARs with incremental 2x higher speed ranges (PWM-G2 to G7), and one GEAR below the default speed range (PWM-G0). This GEAR-based architecture and the modulation scheme enable an M-PHY specification to optimally target data rates and power dissipation based on system requirements.
Figure 3: M-PHY Type-I and Type-II Clocking Architectures (Source: MIPI Alliance)
The M-PHY interface can optionally support a high-speed mode (HS-MODE). The HS-MODE includes a default GEAR (HS-G1) and two optional GEARs (HS-G2 and HS-G3) at incremental 2x higher rates. For any given supported HS GEAR, all lower HS GEARs must always be supported e.g. support for HS-G3 alone is not allowed. Each GEAR includes two baud rates for EMI mitigation reasons, e.g. HS-G1 supports 1.25Gbps and 1.45Gbps. This is especially useful for supporting one handset sold in two geographical regions, which have different base-band frequencies; if one region with a particular base-band frequency suffers beating interference from PHY EMI the alternate rate may be selected.
The G2 and G3 GEARS would operate at 2.5Gb/s and 5Gb/s respectively. Type-II uses a shared reference clock and thus does not require clock recovery. Between the architecture and the clocking options, the M-PHY specification enables the construction of a very versatile set of PHY operations that can target many different LINK requirements. The M-PHY definition is a complete “script”, in specification form, ready for "staging," in silicon, and capable of handling the speed and power requirements of the next generation of mobile devices.