The MIPI Alliance
was created in 2003 to benefit the entire mobile industry by establishing standards for hardware and software interfaces in mobile devices. One critical component of any mobile device is the physical layer (PHY). The first PHY specification that the MIPI Alliance released in 2009 was the D-PHY. The D-PHY currently operates up to 1Gbps and supports both camera serial interface (CSI-2) and display serial interface (DSI), which are increasingly used in both feature and smart phones.
To enable next generation smart phones and tablets, the MIPI Alliance is releasing the M-PHY®1.0 specification by second quarter of 2011, and plans to release versions 2.0 and 3.0 later in the year to support data rates up to 6Gbps at considerably low power. The M-PHY is the most versatile PHY specification available for adoption today.
Benefits and challenges, two faces of the same coin
The M-PHY supports plesiochronous
as well as mesochronous
operations, speeds from 10Kbps up to data rates of 6Gbps while maintaining low power operation, achieving low electro-magnetic-interference (EMI), supporting a variable number of links, sub-links, and data lanes, multiple media options, and a growing number of use-case in traditional and non-traditional mobile applications.
Flexibility and speed
The M-PHY supports two types of operations. Type-I M-PHY supports plesiochronous operation where the PHY on the two sides of the link can operate at slightly different data rates and mesochronous operation where the PHY on both sides of the link use the same reference clock. Type-II supports mesochronous operation only. The high level block diagrams of the two types are shown in Figure 1. This allows use-cases where the reference clock is available on both sides of the link, such as DigRF, to use a simpler more optimized PHY, while also accommodating other use-cases.
Figure 1: M-PHY Type I and Type II clocking architecture / Source: MIPI Alliance
One of the critical features demonstrating the M-PHY versatility is its ability to operate over a wide data range, as low as 10kbps and as high as 5.8Gbps. Additionally the M-PHY state machine allows dynamic transition over this wide data rate range with minimal overhead. The implementer is then able to use the minimum possible amount of power for any particular task and application. The M-PHY accomplished this by supporting 3 different high-speed (HS) gears, 1 through 3 (G1-G3), as shown in Table 1, and multiple low-speed (LS) options, as shown in Figure 2.
Table 1: M-PHY supported data rates / Source: MIPI Alliance
Figure 2: M-PHY Type-I and Type-II Gears / Source: MIPI Alliance
For TYPE-I M-PHY, the specification makes available eight different LS Gears (G0-G7), starting at 10kbps up to 576Mbp, using pulse-width-modulation (PWM). Since the clock is embedded in PWM data, no clock/data recovery (CDR) or even a PLL is needed in this low-speed, low-power mode of operation. For TYPE-II there is no need to use PWM since the same reference clock is available on both sides of the link and thus a less noisy and simpler LS operation is possible (see MIPI-M-PHY takes center stage