Deterministic Latency – Three New Device Subclasses in JESD204B
In the context of JESD204B, deterministic latency is measured from the parallel frame-based data input of a TX device (typically an ADC), to the parallel frame-based data output of an RX device (typically a DAC), measured within the frame clock domain. JESD204B latency is defined (and is programmable) in units of frame clock cycles or periods. The latency must be precisely repeatable from power-up cycle to power-up cycle, and across link resynchronization events.
JESD204B defines three normative Device Subclasses with respect to Deterministic Latency / Harmonic Clocking (DLHC):
Device Subclass 0
has no support for deterministic latency.
Device Subclass 1
defines a new source-synchronous “SYSREF signaling” high-resolution timing (deterministic up to approximately 2 GHz sample clock frequencies) DLHC protocol, with either a periodic SYSREF, a one-shot (strobe-type) SYSREF or a “gapped periodic” SYSREF distributed to all ADCs/DACs and ASIC/FPGA logic devices. The SYSREF signal synchronizes system-wide the local TX and RX frame and multi-frame counters/dividers and the reading of RX FIFO output buffers in JESD204B.
Device Subclass 2
uses the legacy SYNC~ signal, but in a system-synchronous “SYNC~ sampling” low-resolution timing DLHC protocol. This provides accurate deterministic latency up to approximately 500 MHz sample frequencies, utilizing SYNC~ de-assertion to phase adjust ADC, DAC and logic device frame clock and multi-frame clock counters/dividers (combined with control interface based triggering). The SYNC~ signal conveys interface latency timing information in JESD204B, from the receiver back to the transmitter.
JESD204B defines new physical clock signals:
= A global master clock signal synthesized by a system clock generator circuit from which all TX and RX devices (data converters and logic devices) generate their internal frame clock and multi-frame clock signals. The device clock period is the absolute timing reference in a JESD204B system. Note that the device clock signal can be a harmonic multiple of the frame clock; this relates directly to the Harmonic Clocking feature of JESD204B.
= A “global” timing reference signal that can be periodic, one-shot (strobe type), or “gapped” periodic and is used to align frame clock and Local Multi-Frame Clock (LMFC) boundaries. SYSREF is an active high signal that is sampled by the rising edge of the device clock. SYSREF is only used in Device Subclass 1 systems. The SYSREF source must be the same as the device clock source, typically a crystal oscillator time base (such as a low jitter TCXO or VCO/PLL)
It is helpful to recall the definition of frame, multi-frame and LMFC from the JEDEC JESD204A specification:
= A set of consecutive octets in which the position of each octet can be identified by reference to a frame alignment signal.
= A set of consecutive frames in which the position of each frame can be identified by
reference to a multi-frame alignment signal.
= Local Multi-Frame Clock.
Harmonic Frame Clocking Simplifies the PCB-Level Clock Synthesis and Distribution Challenge
Simply put, harmonic clocking allows the use of, for example, 2x, 3x, 4x, 5x, 6x, 7x or 8x FS device clock as the only PCB-level data converter clock, without the need for an additional FS-based frame clock. [The recovered clock from the JESD204B differential input data lane signals is used as the data interface "bit clock".] With harmonic clocking (or single clock system architecture) TX and RX devices can generate all internal clocks from a single clock source, provided that the single clock source is a harmonic multiple of the frame clock.
As a practical example, in the case of a high-speed interpolating DAC architecture (assuming an internal PLL is not used), it is typically required to generate a high-quality device clock signal that is 2x, 4x, or 8x the input data rate sample frequency. This same 2x, 4x, or 8x clock can then be used as the device clock for the ADC, where it is internally divided to create the sample clock (FS) and frame clock.
The advantages of single clock system architectures include reduced IC package pin count and lower risk of detrimental clock feed-through (or crosstalk) effects. In general, fewer clocks on the system PCB level reduce the potential for the disturbance of the ADC and DAC analog performance. On the system PCB level, the design engineer has only one data conversion clock to synthesize and distribute.
Unique System Value Enhancements from JESD204A/B
The new JEDEC JESD204A/B data converter interface definition has numerous system-level technical and commercial merits:
Exciting Backwards-Compatible Future Path
- Simplified PCB layout and routing, with the potential for PCB cost reduction (fewer signal layers, smaller PCB form factor, no data lane-to-clock skew management)
- Data converter and FPGA or ASIC pin count reduction, enabling higher channel count per FPGA or ASIC, with the potential for BOM cost reduction
- Increased system performance, enabling higher bandwidth digital signals over fewer PCB traces
- 8B/10B PHY is compatible with fibre optic signalling for long reach applications
- EMI/RFI radiation reduction, with the potential for easier device compliance test approval
- Reduced signal skew management, with the potential for reduced engineering development cost
- No PCB redesign for data converter resolution changes (12-bit to 16-bit), only FPGA logic reconfiguration / recoding, with the potential for reduced engineering development cost and faster end-product qualification.
- Single bit error detection, by virtue of 8B/10B coding, with the potential for increased system reliability
- Multiple time-aligned and phase coherent data converter channels for system designs such as LTE MIMO base stations, with the potential for simplified system design and reduced engineering development cost
- Interoperability with SERDES-based FPGAs, with the major vendors offering compliant IP for their latest cost-effective programmable logic products
- Periodic frame alignment monitoring with the potential to maintain frame alignment without data loss for system reliability and robustness
- Optional data and control symbol scrambling to produce data independence across the JESD204A/B link, with the potential to reduce non-harmonic spurs in the data converter analog domain
- Optional embedded Pseudo Random Bit Sequence (PRBS) generation (TX) and checking (RX) for simplified board-level Built-In Self Test (BIST)
- Elimination of CMOS parallel bus buffers, with BOM reduced and schematic/layout simplification
As base station and other data acquisition and signal synthesis equipment designers drive relentlessly toward lower capital and operating expense goals, JESD204A interface high-speed data converters can help meet those goals. With the enhancements offered by JESD204B, system designers can save even more in the critical metrics of “dollars, watts and square inches,” making this new data converter and logic device digital interface more compelling than ever. With the expected availability of JESD204B data converters in 2H2011, the widespread adoption of this interface in 2012 seems to be assured.
About the Author
Maury Wood is General Manager of the High Speed Converters product line at NXP Semiconductors. Maury served as JEDEC JC-16 JESD204B Task Group Committee Chairman. He has worked in the semiconductor business for more than 20 years, and previously held marketing and application engineering positions at Analog Devices and Cypress Semiconductor.
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